True Accuracy, 16-Bit 12 V/15 V, Serial Input Voltage Output D/A Converter Features: Full 16-bit performance 1 LSB max INL and DNL Output voltage range up to ±14 V On-board reference buffers, eliminating the need for a negative reference Temperature ranges of −40°C to +85°C for A/B version/−40°C to +125°C for W/Y version Controlled output during power-on Settling time of 10 µs to 0.003% Clear function to 0 V Asynchronous update of outputs (LDAC pin) Power-on reset Serial data output for daisy chaining Data readback facility

12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR 71.3 dBFS at 9.7 MHz input 69.0 dBFS at 200 MHz input SFDR 95 dBc at 9.7 MHz input 83 dBc at 200 MHz input Low power 45 mW at 20 MSPS 85 mW at 80 MSPS Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = ±0.16 LSB Serial port control options Offset binary, gray code, or twos complement data format Integer 1, 2, or 4 input clock divider Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock out with programmable clock and data alignment

10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter Features: 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR 61.5 dBFS at 9.7 MHz input 61.0 dBFS at 200 MHz input SFDR 75 dBc at 9.7 MHz input 73 dBc at 200 MHz input Low power 45 mW at 20 MSPS 76 mW at 80 MSPS Differential input with 700 MHz bandwidth On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = ±0.10 LSB Serial port control options Offset binary, gray code, or twos complement data format Optional clock duty cycle stabilizer Integer 1-to-8 input clock divider Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock out with programmable clock and data alignment

Dual, 16-Bit, 1200 MSPS, TxDAC+Digital-to-Analog Converter Features: Flexible LVDS interface allows word, byte, or nibble load Single-carrier W-CDMA ACLR = 82 dBc @ 122.88 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Novel 2×/4×/8× interpolator/complex modulator allows carrier placement anywhere in the DAC bandwidth Digital gain and phase adjustment for sideband suppression Multiple chip synchronization interfaces See data sheet for additional featuresAD9122-EP supports defense and aerospace applications (AQEC standard) Download AD9122-EP data sheet (pdf) Military temperature range (such as −55°C to +105°C) Controlled manufacturing baseline One assembly/test site One fabrication site Enhanced product change notification Qualification data available on request V62/12654 DSCC Drawing Number

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