Junction System Tools & Accessories 10-32 coaxialNote: A22003 = part number for connector only

Junction System Tools & Accessories 10-32 coaxialNote: A22003 = part number for connector only

Development Boards & Kits - ARM BEAGLE BOARD W/DM3730 & HW UPGRADES

4-port USB 3.0 SuperSpeed hub evaluation module

TPS22993EVM-033 Evaluation Module

The ADuCRF101 is a fully integrated, data acquisition solution that is designed for low power, wireless applications. It features a 12-bit analog-to-digital converter (ADC), a low power ARM Cortex?-M3 processor, a 862 MHz to 928 MHz and 431 MHz to 464 MHz RF transceiver, and Flash?/EE memory. The ADuCRF101 is packaged in a 9 mm ? 9 mm LFCSP.The data acquisition section consists of a 12-bit SAR ADC. The six inputs can be configured in single-ended or differential mode. When configured in single-ended mode, they can be used for ratiometric measurements on sensors that are powered, when required, from the internal low dropout regulator (LDO). An internal battery monitor channel and an on-chip temperature sensor are also available.This wireless data acquisition system is designed to operate in battery-powered applications where low power is critical. The device can be configured in normal operating mode or different low power modes under direct program control. In flexi mode, any peripheral can wake up the device and operate it. In hibernate mode, the internal wake-up timer remains active. In shutdown mode, only an external interrupt can wake up the device.The ADuCRF101 integrates a low power ARM Cortex-M3 processor. It is a 32-bit RISC machine, offering up to 1.25 DMIPS peak performance. The ARM Cortex-M3 processor also has a flexible 14-channel direct memory access (DMA) controller that supports communication peripherals, serial peripheral interface (SPI), UART, and I2C. Also provided on chip are 128 kB of nonvolatile Flash/EE memory and 16 kB of SRAM.A 16 MHz on-chip oscillator generates the system clock. This clock can be internally divided for the processor to operate at a lower frequency, thus saving power. A low power, internal 32 kHz oscillator is available and can be used to clock the four timers, as follows: two general-purpose timers, a wake-up timer, and a system watchdog timer.A range of communication peripherals can be configured, as required, in a specific application. These peripherals include UART, I2C, SPI, GPIO ports, PWM, and RF transceivers.The RF transceiver communicates in the 862 MHz to 928 MHz and 431 MHz to 464 MHz frequency bands using multiple configurations.On-chip factory firmware supports in-circuit serial download via the UART, and nonintrusive emulation and program download are also supported via the serial wire interface. These features are incorporated into a low cost development system supporting this precision analog microcontroller family.The ADuCRF101 operates from 2.2 V to 3.6 V and is specified over an industrial temperature range of ?40?C to +85?C. It is available in a 64-lead LFCSP packageApplications Battery powered wireless sensor Medical telemetry systems Industrial and home automation Asset tracking Security systems (access systems) Health and fitness applications??

The AD6657 is an 11-bit, 200 MSPS, quad-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.The device consists of four high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features a wide bandwidth switched-capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the external MODE pin or the SPI.With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6657 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution. The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. For example, with a sample clock rate of 185 MSPS, the AD6657 can achieve up to 75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode.With the NSR block disabled, the ADC data is provided directly to the output with a resolution of 11 bits. The AD6657 can achieve up to 66.5 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6657 to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are desired.After digital signal processing, multiplexed output data is routed into two 11-bit output ports such that the maximum data rate is 400 Mbps (DDR). These outputs are set at 1.8 V LVDS and support ANSI-644 levels.The AD6657 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of a separate antenna. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods.Flexible power-down options allow significant power savings. Programming for device setup and control is accomplished using a 3-wire SPI-compatible serial interface with numerous modes to support board-level system testing.The AD6657 is available in a Pb-free/RoHS compliant, 144-ball, 10 mm ? 10 mm chip scale package ball grid array (CSP_BGA) and is specified over the industrial temperature range of ?40?C to +85?C.APPLICATIONS Communications Diversity radio and smart antenna (MIMO) systems Multimode digital receivers (3G) ?WCDMA, LTE, CDMA2000 ?WiMAX, TD-SCDMA I/Q demodulation systems General-purpose software radiosPRODUCT HIGHLIGHTS Four ADCs are contained in a small, space-saving, 10 mm ? 10 mm ? 1.4 mm, 144-ball CSP_BGA package. Pin selectable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of up to 60 MHz at 185 MSPS. LVDS digital output interface configured for low cost FPGA families. 230 mW per ADC core power consumption. Operation from a single 1.8 V supply. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary or twos complement), NSR, power-down, test modes, and voltage reference mode. On-chip integer 1-to-8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems.

TPS63051EVM-180 Buck Boost Regulator Evaluation Module

The TPS65982-EVM is a complete reference design for USB Type-C and Power Delivery applications. It allows the user to develop various power profiles and alternate modes such as DisplayPort and debug existing USB Type-C and Power Delivery systems.

 

 

Features:

• USB Type-C testing and verification
• USB Power Delivery testing and verification
• Application Emulation (Notebook, Dock, Dongle, Charger)
• Powered from single supply and bus-powered capable

This EVM was developed prior to the USB Power Delivery Specification change back in March 2016 and therefore does not have the native hardware to support the 5, 9, 15 and 20V rails. In order to follow the new source power rules please refer to TPS65982 Designs for Supporting Voltages in USB-PD 'Power Rules' or reference the TPS65981EVM.

Motor Driver Solutions and Evaluation Modules for Non-Safety Critical Automotive Applications