The ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E are 3.0 V to5.5 V, IEC electrostatic discharge (ESD) protected RS-485transceivers, allowing the devices to withstand ?12 kV contactdischarges on the transceiver bus pins without latch-up ordamage. The ADM3062E/ADM3064E/ADM3066E/ADM3068Efeature a VIO logic supply pin that allows a flexible digital interfacecapable of operating as low as 1.62 V. The ADM3065E/ADM3066E/ADM3067E/ADM3068E aresuitable for high speed, 50 Mbps, bidirectional data communication on multipoint bus transmission lines. The ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E feature a 1/4 unit load inputimpedance that allows up to 128 transceivers on a bus. TheADM3061E/ADM3062E/ADM3063E/ADM3064E models offerall of the same features as the ADM3065E/ADM3066E/ADM3067E/ADM3068E models at a low 500 kbps data rate thatis suitable for operation over long cable runs. The ADM3061E/ADM3062E/ADM3065E/ADM3066E are halfduplex RS-485 transceivers, fully compliant to the PROFIBUS?standard with increased 2.1 V bus differential voltage at VCC ?4.5 V. The ADM3063E/ADM3064E/ADM3067E/ADM3068Eare full duplex RS-485 transceiver options. The RS-485 transceivers are available in a number of spacesaving packages, including the 10-lead, 3 mm ? 3 mm lead framechip-scale package (LFCSP), the 8-lead or 10-lead, 3 mm ? 3 mmmini small outline package (MSOP), and the 8-lead or 14-lead,narrow body standard small outline packages (SOIC_N).Models with operating temperature ranges of ?40?C to +125?Cand ?40?C to +85?C are available. Excessive power dissipation caused by bus contention or byoutput shorting is prevented by a thermal shutdown circuit. If asignificant temperature increase is detected in the internal drivercircuitry during fault conditions, this feature forces the driveroutput into a high impedance state. The ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E guarantee alogic high receiver output when the receiver inputs are shorted,open, or connected to a terminated transmission line with alldrivers disabled. Table 2 in the data sheet presents an overview of the ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E data rate capability across temperature, power supply,and package options. Refer to the Ordering Guide section formodel numbering.APPLICATIONS Industrial fieldbuses Process control Building automation PROFIBUS networks Motor control servo drives and encoders?

The ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E are 3.0 V to5.5 V, IEC electrostatic discharge (ESD) protected RS-485transceivers, allowing the devices to withstand ?12 kV contactdischarges on the transceiver bus pins without latch-up ordamage. The ADM3062E/ADM3064E/ADM3066E/ADM3068Efeature a VIO logic supply pin that allows a flexible digital interfacecapable of operating as low as 1.62 V. The ADM3065E/ADM3066E/ADM3067E/ADM3068E aresuitable for high speed, 50 Mbps, bidirectional data communication on multipoint bus transmission lines. The ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E feature a 1/4 unit load inputimpedance that allows up to 128 transceivers on a bus. TheADM3061E/ADM3062E/ADM3063E/ADM3064E models offerall of the same features as the ADM3065E/ADM3066E/ADM3067E/ADM3068E models at a low 500 kbps data rate thatis suitable for operation over long cable runs. The ADM3061E/ADM3062E/ADM3065E/ADM3066E are halfduplex RS-485 transceivers, fully compliant to the PROFIBUS?standard with increased 2.1 V bus differential voltage at VCC ?4.5 V. The ADM3063E/ADM3064E/ADM3067E/ADM3068Eare full duplex RS-485 transceiver options. The RS-485 transceivers are available in a number of spacesaving packages, including the 10-lead, 3 mm ? 3 mm lead framechip-scale package (LFCSP), the 8-lead or 10-lead, 3 mm ? 3 mmmini small outline package (MSOP), and the 8-lead or 14-lead,narrow body standard small outline packages (SOIC_N).Models with operating temperature ranges of ?40?C to +125?Cand ?40?C to +85?C are available. Excessive power dissipation caused by bus contention or byoutput shorting is prevented by a thermal shutdown circuit. If asignificant temperature increase is detected in the internal drivercircuitry during fault conditions, this feature forces the driveroutput into a high impedance state. The ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E guarantee alogic high receiver output when the receiver inputs are shorted,open, or connected to a terminated transmission line with alldrivers disabled. Table 2 in the data sheet presents an overview of the ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E data rate capability across temperature, power supply,and package options. Refer to the Ordering Guide section formodel numbering.APPLICATIONS Industrial fieldbuses Process control Building automation PROFIBUS networks Motor control servo drives and encoders?

The ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E are 3.0 V to5.5 V, IEC electrostatic discharge (ESD) protected RS-485transceivers, allowing the devices to withstand ?12 kV contactdischarges on the transceiver bus pins without latch-up ordamage. The ADM3062E/ADM3064E/ADM3066E/ADM3068Efeature a VIO logic supply pin that allows a flexible digital interfacecapable of operating as low as 1.62 V. The ADM3065E/ADM3066E/ADM3067E/ADM3068E aresuitable for high speed, 50 Mbps, bidirectional data communication on multipoint bus transmission lines. The ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E feature a 1/4 unit load inputimpedance that allows up to 128 transceivers on a bus. TheADM3061E/ADM3062E/ADM3063E/ADM3064E models offerall of the same features as the ADM3065E/ADM3066E/ADM3067E/ADM3068E models at a low 500 kbps data rate thatis suitable for operation over long cable runs. The ADM3061E/ADM3062E/ADM3065E/ADM3066E are halfduplex RS-485 transceivers, fully compliant to the PROFIBUS?standard with increased 2.1 V bus differential voltage at VCC ?4.5 V. The ADM3063E/ADM3064E/ADM3067E/ADM3068Eare full duplex RS-485 transceiver options. The RS-485 transceivers are available in a number of spacesaving packages, including the 10-lead, 3 mm ? 3 mm lead framechip-scale package (LFCSP), the 8-lead or 10-lead, 3 mm ? 3 mmmini small outline package (MSOP), and the 8-lead or 14-lead,narrow body standard small outline packages (SOIC_N).Models with operating temperature ranges of ?40?C to +125?Cand ?40?C to +85?C are available. Excessive power dissipation caused by bus contention or byoutput shorting is prevented by a thermal shutdown circuit. If asignificant temperature increase is detected in the internal drivercircuitry during fault conditions, this feature forces the driveroutput into a high impedance state. The ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E guarantee alogic high receiver output when the receiver inputs are shorted,open, or connected to a terminated transmission line with alldrivers disabled. Table 2 in the data sheet presents an overview of the ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E data rate capability across temperature, power supply,and package options. Refer to the Ordering Guide section formodel numbering.APPLICATIONS Industrial fieldbuses Process control Building automation PROFIBUS networks Motor control servo drives and encoders?

The ADN2812 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 automatically locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for ?40?C to +85?C ambient temperature, unless otherwise noted. This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power fiber optic receiver. The receiver front end, loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a user-adjustable threshold. The LOS detect circuit has hysteresis to prevent chatter at the output. The ADN2812 is available in a compact 5 mm ? 5 mm 32-lead lead frame chip scale package (LFCSP).ApplicationsSONET OC-1/OC-3/OC-12/OC-48 and all associated FEC rates Fibre Channel, 2? Fibre Channel, GbE, HDTV WDM transponders Regenerators/repeaters Test equipment Broadband cross-connects and routers

The ADN2816 provides the receiver functions of quantization and clock and data recovery for continuous data rates from 10 Mb/s to 675 Mb/s. The ADN2816 automatically locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for ?40?C to +85?C ambient temperature, unless otherwise noted.The ADN2816 is available in a compact 5 mm ? 5 mm 32-lead chip scale package.ApplicationsSONET OC-1/3/12 and all associated FEC rates Fibre Channel, ESCON, Fast Ethernet, SDI, etc. WDM transpondersRegenerators/repeatersTest equipmentBroadband cross-connects and routers

The ADN2850 is a dual-channel, nonvolatile memory, digitallycontrolled resistors?with 1024-step resolution, offeringguaranteed maximum low resistor tolerance error of ?8%. Thedevice performs the same electronic adjustment function as amechanical rheostat with enhanced resolution, solid statereliability, and superior low temperature coefficientperformance. The versatile programming of the ADN2850 viaan SPI?-compatible serial interface allows 16 modes ofoperation and adjustment including scratchpad programming,memory storing and restoring, increment/decrement, ?6 dB/steplog taper adjustment, wiper setting readback, and extra EEMEM?for user-defined information such as memory data for other components, look-up table, or system identificationinformation.In the scratchpad programming mode, a specific setting canbe programmed directly to the RDAC?register, which sets theresistance between Terminal W and Terminal B. This setting canbe stored into the EEMEM and is restored automatically to theRDAC register during system power-on.The EEMEM content can be restored dynamically or throughexternal PR strobing, and a WP function protects EEMEM contents. To simplify the programming, the independent orsimultaneous linear-step increment or decrement commandscan be used to move the RDAC wiper up or down, one step at atime. For logarithmic ?6 dB changes in the wiper setting, theleft or right bit shift command can be used to double or halve theRDAC wiper setting.The ADN2850 patterned resistance tolerance is stored in theEEMEM. The actual full scale resistance can, therefore, beknown by the host processor in readback mode. The host canexecute the appropriate resistance step through a softwareroutine that simplifies open-loop applications as well asprecision calibration and tolerance matching applications.The ADN2850 is available in the 5 mm ? 5 mm 16-lead framechip scale LFCSP and thin, 16-lead TSSOP package. The part isguaranteed to operate over the extended industrial temperaturerange of ?40?C to +85?C.Applications SONET, SDH, ATM, Gigabit Ethernet, DWDM laser diode driver, optical supervisory systems Mechanical rheostat replacement Instrumentation gain adjustment Programmable filters, delays, time constants Sensor calibration

The ADN4620/ADN4621 are dual-channel, signal isolated, low voltage differential signaling (LVDS) buffers that operate at up to 2.5 Gbps with very low jitter. The devices integrate Analog Devices, Inc., iCoupler? technology, enhanced for high speed operation to provide drop-in galvanic isolation of LVDS signal chains. AC coupling and/or level shifting to the LVDS receivers and from the LVDS drivers allows isolation of other high speed signals, such as current mode logic (CML).The ADN4620/ADN4621 include a refresh mechanism to monitor the input and output states and ensure that they remain the same in the absence of data transitions (for example, at power-on). For lower power consumption and high speed operation with low jitter, the isolator circuits rely on 1.8 V supplies, while 3.3 V supplies are used for LVDS receivers to support the full common-mode range with an input voltage range (input common mode plus differential input voltage) of 0 V to 2.4 V per Table 2 in the data sheet.The devices are fully specified over a wide industrial temperature range and are available in a compact SSOP package with 5.3 mm creepage (for reinforced insulation at ac mains voltages).APPLICATIONS Analog front-end isolation Data plane isolation Isolated high speed clock and data links Multigigabit serialization/deserialization (SERDES) PCB-to-PCB optical replacement (for example, short reach fiber)Protected by U.S. Patents 7,075,329; 9,941,565; and 10,205,442. Other patents are pending.

The ADN4654/ADN4655/ADN46561? are signal isolated, low voltage differential signaling (LVDS) buffers that operate at up to 1.1 Gbps with low jitter. The devices integrate Analog Devices, Inc., iCoupler? technology, enhanced for high speed operation to provide galvanic isolation of the TIA/EIA-644-A compliant LVDS drivers and receivers. This integration allows drop-in isolation of an LVDS signal chain.The ADN4654/ADN4655/ADN4656 comprise multiple channel configurations, and the LVDS receivers on the ADN4655 and ADN4656 include a fail-safe mechanism to ensure a Logic 1 on the corresponding LVDS driver output when the inputs are floating, shorted, or terminated but not driven.For high speed operation with low jitter, the LVDS and isolator circuits rely on a 2.5 V supply. An integrated on-chip low dropout (LDO) regulator can provide the required 2.5 V from an external 3.3 V power supply. The devices are fully specified over a wide industrial temperature range and come in a 20-lead, wide body SOIC_W package with 5 kV rms isolation or in a 20-lead SSOP package with 3.75 kV rms isolation.Applications Isolated video and imaging data Analog front-end isolation Data plane isolation Isolated high speed clock and data links1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.

The ADN4654/ADN4655/ADN46561? are signal isolated, low voltage differential signaling (LVDS) buffers that operate at up to 1.1 Gbps with low jitter. The devices integrate Analog Devices, Inc., iCoupler? technology, enhanced for high speed operation to provide galvanic isolation of the TIA/EIA-644-A compliant LVDS drivers and receivers. This integration allows drop-in isolation of an LVDS signal chain.The ADN4654/ADN4655/ADN4656 comprise multiple channel configurations, and the LVDS receivers on the ADN4655 and ADN4656 include a fail-safe mechanism to ensure a Logic 1 on the corresponding LVDS driver output when the inputs are floating, shorted, or terminated but not driven.For high speed operation with low jitter, the LVDS and isolator circuits rely on a 2.5 V supply. An integrated on-chip low dropout (LDO) regulator can provide the required 2.5 V from an external 3.3 V power supply. The devices are fully specified over a wide industrial temperature range and come in a 20-lead, wide body SOIC_W package with 5 kV rms isolation or in a 20-lead SSOP package with 3.75 kV rms isolation.Applications Isolated video and imaging data Analog front-end isolation Data plane isolation Isolated high speed clock and data links1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.

The ADPD6000 is a highly integrated analog front end (AFE) designed for measuring various vital signals.The optical channel is designed as an optical transceiver, stimulating up to four light emitting diodes (LEDs) and measuring the return signal on up to four separate current inputs. The signal chain rejects signal offsets and corruption from asynchronous modulated interference, typically from ambient light, eliminating the need for optical filters or externally controlled dc cancellation circuitry.The electrocardiography (ECG) signal acquisition is designed to support low noise, diagnostic level measurement in the presence of a variety of interferers. The ECG signal chain has a number of complementary features supporting ECG measurement, such as driven reference for common-mode rejection and lead off detection to identify a fallen electrode.The body impedance analysis (BIA) signal chain is designed for body impedance measurement with a configurable excitation path and measurement path. A 12-bit digital-to-analog (DAC) is used in the excitation path to generate the sinusoid wave and high precision measurement, with configurable filters used to measure the body response of the stimulus.The data output and functional configuration use a serial port interface (SPI) on the ADPD6000. The control circuitry includes flexible LED signaling and synchronous detection, digital filters, digital wave generators, and configurable filters.The ADPD6000 is available in a 2.6 mm ? 2.6 mm, 0.4 mm pitch, 36-ball wafer level chip scale package (WLCSP).APPLICATIONS Wearable health and fitness monitors: heart rate, heart rate variability, SpO2, body impedance analysis, hydration, cuffless noninvasive blood pressure Home patient monitoring Industrial monitoring: particle and aerosol, gas, and conductivity detection