The ADN2812 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 automatically locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for ?40?C to +85?C ambient temperature, unless otherwise noted. This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power fiber optic receiver. The receiver front end, loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a user-adjustable threshold. The LOS detect circuit has hysteresis to prevent chatter at the output. The ADN2812 is available in a compact 5 mm ? 5 mm 32-lead lead frame chip scale package (LFCSP).ApplicationsSONET OC-1/OC-3/OC-12/OC-48 and all associated FEC rates Fibre Channel, 2? Fibre Channel, GbE, HDTV WDM transponders Regenerators/repeaters Test equipment Broadband cross-connects and routers

The ADN2850 is a dual-channel, nonvolatile memory, digitallycontrolled resistors?with 1024-step resolution, offeringguaranteed maximum low resistor tolerance error of ?8%. Thedevice performs the same electronic adjustment function as amechanical rheostat with enhanced resolution, solid statereliability, and superior low temperature coefficientperformance. The versatile programming of the ADN2850 viaan SPI?-compatible serial interface allows 16 modes ofoperation and adjustment including scratchpad programming,memory storing and restoring, increment/decrement, ?6 dB/steplog taper adjustment, wiper setting readback, and extra EEMEM?for user-defined information such as memory data for other components, look-up table, or system identificationinformation.In the scratchpad programming mode, a specific setting canbe programmed directly to the RDAC?register, which sets theresistance between Terminal W and Terminal B. This setting canbe stored into the EEMEM and is restored automatically to theRDAC register during system power-on.The EEMEM content can be restored dynamically or throughexternal PR strobing, and a WP function protects EEMEM contents. To simplify the programming, the independent orsimultaneous linear-step increment or decrement commandscan be used to move the RDAC wiper up or down, one step at atime. For logarithmic ?6 dB changes in the wiper setting, theleft or right bit shift command can be used to double or halve theRDAC wiper setting.The ADN2850 patterned resistance tolerance is stored in theEEMEM. The actual full scale resistance can, therefore, beknown by the host processor in readback mode. The host canexecute the appropriate resistance step through a softwareroutine that simplifies open-loop applications as well asprecision calibration and tolerance matching applications.The ADN2850 is available in the 5 mm ? 5 mm 16-lead framechip scale LFCSP and thin, 16-lead TSSOP package. The part isguaranteed to operate over the extended industrial temperaturerange of ?40?C to +85?C.Applications SONET, SDH, ATM, Gigabit Ethernet, DWDM laser diode driver, optical supervisory systems Mechanical rheostat replacement Instrumentation gain adjustment Programmable filters, delays, time constants Sensor calibration

The ADN4620/ADN4621 are dual-channel, signal isolated, low voltage differential signaling (LVDS) buffers that operate at up to 2.5 Gbps with very low jitter. The devices integrate Analog Devices, Inc., iCoupler? technology, enhanced for high speed operation to provide drop-in galvanic isolation of LVDS signal chains. AC coupling and/or level shifting to the LVDS receivers and from the LVDS drivers allows isolation of other high speed signals, such as current mode logic (CML).The ADN4620/ADN4621 include a refresh mechanism to monitor the input and output states and ensure that they remain the same in the absence of data transitions (for example, at power-on). For lower power consumption and high speed operation with low jitter, the isolator circuits rely on 1.8 V supplies, while 3.3 V supplies are used for LVDS receivers to support the full common-mode range with an input voltage range (input common mode plus differential input voltage) of 0 V to 2.4 V per Table 2 in the data sheet.The devices are fully specified over a wide industrial temperature range and are available in a compact SSOP package with 5.3 mm creepage (for reinforced insulation at ac mains voltages).APPLICATIONS Analog front-end isolation Data plane isolation Isolated high speed clock and data links Multigigabit serialization/deserialization (SERDES) PCB-to-PCB optical replacement (for example, short reach fiber)Protected by U.S. Patents 7,075,329; 9,941,565; and 10,205,442. Other patents are pending.

The ADN4624 is a quad-channel, signal isolated, low voltage differential signaling (LVDS) buffer that operates at up to 2.5 Gbps with very low jitter. The device integrates Analog Devices, Inc., iCoupler? technology, enhanced for high speed operation to provide drop-in galvanic isolation of LVDS signal chains. AC coupling and/or level shifting to the LVDS receivers and from the LVDS drivers allows isolation of other high speed signals such as current mode logic (CML).The ADN4624 includes a refresh mechanism to monitor the input and output states and ensure they remain the same in the absence of data transitions (for example, at power-on).For lower power consumption and high speed operation with low jitter, the LVDS and isolator circuits rely on 1.8 V supplies. The ADN4624 is fully specified over a wide industrial temperature range and is available in a 28-lead, wide-body, finer pitch SOIC_W_FP package with 8.3 mm creepage and clearance (for 5.7 kV rms or 8 kVPEAK surge and impulse voltages and reinforced insulation at ac mains voltages) or 6 mm ? 6 mm LFCSP package with 1.27 mm creepage and clearance (for basic/functional isolation).APPLICATIONS Isolated video and imaging data Analog front-end isolation Data plane isolation Isolated high speed clock and data links Multi-gigabit serialization/deserialization (SERDES) Board-to-board optical replacement (for example, short reach fiber)

The ADN4654/ADN4655/ADN46561? are signal isolated, low voltage differential signaling (LVDS) buffers that operate at up to 1.1 Gbps with low jitter. The devices integrate Analog Devices, Inc., iCoupler? technology, enhanced for high speed operation to provide galvanic isolation of the TIA/EIA-644-A compliant LVDS drivers and receivers. This integration allows drop-in isolation of an LVDS signal chain.The ADN4654/ADN4655/ADN4656 comprise multiple channel configurations, and the LVDS receivers on the ADN4655 and ADN4656 include a fail-safe mechanism to ensure a Logic 1 on the corresponding LVDS driver output when the inputs are floating, shorted, or terminated but not driven.For high speed operation with low jitter, the LVDS and isolator circuits rely on a 2.5 V supply. An integrated on-chip low dropout (LDO) regulator can provide the required 2.5 V from an external 3.3 V power supply. The devices are fully specified over a wide industrial temperature range and come in a 20-lead, wide body SOIC_W package with 5 kV rms isolation or in a 20-lead SSOP package with 3.75 kV rms isolation.Applications Isolated video and imaging data Analog front-end isolation Data plane isolation Isolated high speed clock and data links1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.

The ADN4654/ADN4655/ADN46561? are signal isolated, low voltage differential signaling (LVDS) buffers that operate at up to 1.1 Gbps with low jitter. The devices integrate Analog Devices, Inc., iCoupler? technology, enhanced for high speed operation to provide galvanic isolation of the TIA/EIA-644-A compliant LVDS drivers and receivers. This integration allows drop-in isolation of an LVDS signal chain.The ADN4654/ADN4655/ADN4656 comprise multiple channel configurations, and the LVDS receivers on the ADN4655 and ADN4656 include a fail-safe mechanism to ensure a Logic 1 on the corresponding LVDS driver output when the inputs are floating, shorted, or terminated but not driven.For high speed operation with low jitter, the LVDS and isolator circuits rely on a 2.5 V supply. An integrated on-chip low dropout (LDO) regulator can provide the required 2.5 V from an external 3.3 V power supply. The devices are fully specified over a wide industrial temperature range and come in a 20-lead, wide body SOIC_W package with 5 kV rms isolation or in a 20-lead SSOP package with 3.75 kV rms isolation.Applications Isolated video and imaging data Analog front-end isolation Data plane isolation Isolated high speed clock and data links1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.

The ADPD105/ADPD106/ADPD107 are highly efficient,photometric front ends, each with an integrated 14-bit analog-to-digitalconverter (ADC) and a 20-bit burst accumulator thatworks with flexible light emitting diode (LED) drivers. Theaccumulator is designed to stimulate an LED and measurethe corresponding optical return signal. The data output andfunctional configuration occur over a 1.8 V I2C interface on theADPD105 or SPI on the ADPD106 and ADPD107. The controlcircuitry includes flexible LED signaling and synchronousdetection.The analog front end (AFE) features best-in-class rejection of signaloffset and corruption due to modulated interference commonlycaused by ambient light.Couple the ADPD105/ADPD106/ADPD107 with a lowcapacitance photodiode of <100 pF for optimal performance.The ADPD105/ADPD106/ADPD107 can be used with any LED.The ADPD105 is available in a 2.46 mm ? 1.4 mm WLCSP and a4 mm ? 4 mm LFCSP. The SPI only versions, ADPD106 andADPD107, are available in a 2.46 mm ? 1.4 mm WLCSP.Applications Wearable health and fitness monitors Clinical measurements, for example, SpO2 Industrial monitoring Background light measurements

The ADT7310 is a high accuracy digital temperature sensor in a narrow SOIC package. It contains a band gap temperature reference and a 13-bit ADC to monitor and digitize the temperature to a 0.0625?C resolution. The ADC resolution, by default, is set to 13 bits (0.0625 ?C). This can be changed to 16 bits (0.0078 ?C) by setting Bit 7 in the configuration register (Register Address 0x01).The ADT7310 is guaranteed to operate over supply voltages from 2.7 V to 5.5 V. Operating at 3.3 V, the average supply current is typically 210 ?A. The ADT7310 has a shutdown mode that powers down the device and offers a shutdown current of typically 2 ?A. The ADT7310 is rated for operation over the ?55?C to +150?C temperature range.The CT pin is an open-drain output that becomes active when the temperature exceeds a programmable critical temperature limit. The default critical temperature limit is 147?C. The INT pin is also an open-drain output that becomes active when the temperature exceeds a programmable limit. The INT and CT pins can operate in either comparator or interrupt mode.APPLICATIONS Medical equipment Environmental control systems Computer thermal monitoring Thermal protection Industrial process control Power system monitors Hand-held applications

The ADT7420 is a high accuracy digital temperature sensoroffering breakthrough performance over a wide industrialrange, housed in a 4 mm ? 4 mm LFCSP package. It contains aninternal band gap reference, a temperature sensor, and a 16-bitADC to monitor and digitize the temperature to 0.0078?Cresolution. The ADC resolution, by default, is set to 13 bits(0.0625?C). The ADC resolution is a user programmable modethat can be changed through the serial interface.The ADT7420 is guaranteed to operate over supply voltages from2.7 V to 5.5 V. Operating at 3.3 V, the average supply current is typically210 ?A. The ADT7420 has a shutdown mode that powersdown the device and offers a shutdown current of typically 2.0 ?Aat 3.3 V. The ADT7420 is rated for operation over the ?40?C to+150?C temperature range.Pin A0 and Pin A1 are available for address selection, giving theADT7420 four possible I2C addresses. The CT pin is an open-drainoutput that becomes active when the temperature exceedsa programmable critical temperature limit. The INT pin is alsoan open-drain output that becomes active when the temperatureexceeds a programmable limit. The INT pin and CT pincan operate in comparator and interrupt event modes.Product Highlights Ease of use, no calibration or correction required by the user. Low power consumption. Excellent long-term stability and reliability. High accuracy for industrial, instrumentation, and medical applications. Packaged in a 16-lead, 4 mm ? 4 mm LFCSP RoHS-compliant package.Applications RTD and thermistor replacement Thermocouple cold junction compensation Medical equipment Industrial control and test Food transportation and storage Environmental monitoring and HVAC Laser diode temperature control

The ADuC7019?/?ADuC7020?/ ADuC7021 /?ADuC7022?/?ADuC7024?/?ADuC7025?/ ADuC7026?/?ADuC7027?/?ADuC7028?/?ADuC7029 are fully integrated,1 MSPS, 12-bit data acquisition systems incorporating highperformance multichannel ADCs, 16-bit/32-bit MCUs, andFlash?/EE memory on a single chip.The ADC consists of up to 12 single-ended inputs. An additionalfour inputs are available but are multiplexed with the four DACoutput pins. The four DAC outputs are available only on certainmodels (ADuC7020, ADuC7026, ADuC7028, and ADuC7029).However, in many cases where the DAC outputs are not present,these pins can still be used as additional ADC inputs, giving amaximum of 16 ADC input channels. The ADC can operate insingle-ended or differential input mode. The ADC input voltageis 0 V to VREF. A low drift band gap reference, temperature sensor,and voltage comparator complete the ADC peripheral set.Depending on the part model, up to four buffered voltageoutput DACs are available on-chip. The DAC output range isprogrammable to one of three voltage ranges.The devices operate from an on-chip oscillator and a PLLgenerating an internal high frequency clock of 41.78 MHz(UCLK). This clock is routed through a programmable clockdivider from which the MCU core clock operating frequencyis generated. The microcontroller core is an ARM7TDMI?,16-bit/32-bit RISC machine, which offers up to 41 MIPS peakperformance. Eight kilobytes of SRAM and 62 kilobytes ofnonvolatile Flash/EE memory are provided on-chip. TheARM7TDMI core views all memory and registers as a singlelinear array.On-chip factory firmware supports in-circuit serial downloadvia the UART or I2C serial interface port; nonintrusive emulationis also supported via the JTAG interface. These features areincorporated into a low cost QuickStart? development systemsupporting this MicroConverter? family.The parts operate from 2.7 V to 3.6 V and are specified over anindustrial temperature range of ?40?C to +125?C. Whenoperating at 41.78 MHz, the power dissipation is typically120 mW. The ADuC7019 / ADuC7020 / ADuC7021 /? ADuC7022 / ADuC7024 / ADuC7025 / ADuC7026 / ADuC7027 / ADuC7028 / ADuC7029 areavailable in a variety of memory models and packages (seeOrdering Guide).APPLICATIONS Industrial control and automation systems Smart sensors, precision instrumentation Base station systems, optical networking