The high performance ADXL350 is a small, thin, low power,3-axis accelerometer with high resolution (13-bit) and selectablemeasurement ranges up to ?8?g. The ADXL350 offers industry-leading temperature performance with guaranteed min/max specification for offset over temperature. Digital output data isformatted as 16-bit twos complement and is accessible througheither a SPI (3- or 4-wire) or I2C digital interface.The ADXL350 is well suited for high performance portableapplications. It measures the static acceleration of gravity in tilt sensingapplications, as well as dynamic acceleration resultingfrom motion or shock. Its high resolution (2 mg/LSB) enablesmeasurement of inclination changes of less than 1.0?.Several special sensing functions are provided. Activity andinactivity sensing detect the presence or lack of motion and ifthe acceleration on any axis exceeds a user-set level. Tap sensingdetects single and double taps. Free-fall sensing detects if thedevice is falling. These functions can be mapped to one of twointerrupt output pins.Low power modes enable intelligent motion-based powermanagement with threshold sensing and active accelerationmeasurement at extremely low power dissipation.The ADXL350 is supplied in a small, thin, 3 mm ? 4 mm ?1.2 mm, 16-lead cavity laminate package.APPLICATIONS Portable Consumer Devices High performance medical and industrial applications

The EVAL-ADXL367Z is a simple breakout board that enables easy connection of an ADXL367 into an existing system. The ADXL367 is a nanowatt, 3-axis, digital-output accelerometer whose industry leading low power consumption and built-in features make it ideal for use in a wide variety of applications. Due to its small size, the EVAL-ADXL367Z has minimal effect on performance of the system and of the accelerometer, and thus it is ideal for evaluation of the ADXL367 in an existing system. Note that the ADXL367 must be communicated with digitally via SPI or I2C. No processor is included with the EVAL-ADXL367Z; firmware must be supplied externally by the user. For evaluation boards that include a processor, please see the EVAL-ADXL367-SDP. MARKETS & TECHNOLOGY Industrial Digital Healthcare Prosumer Automotive Aerospace and Defense

The ADXL375 is a small, thin, 3-axis MEMS accelerometer that provides low power consumption and high resolution measurement up to ?200?g. The digital output data is formatted as 16-bit, twos complement data and is accessible through a SPI (3- or 4-wire) or I2C digital interface.An integrated memory management system with a 32-level first in, first out (FIFO) buffer can be used to store data to minimize host processor activity and lower overall system power consumption.Low power modes enable intelligent motion-based power management with threshold sensing and active acceleration measurement at extremely low power dissipation.The ADXL375 is supplied in a small, thin, 3 mm ? 5 mm ? 1 mm, 14-lead LGA.APPLICATIONS Concussion and head trauma detection High force event detection

KSZ8895RQX EVAL BOARD

The ADRF5044 is a general-purpose, single-pole, four-throw (SP4T) switch manufactured using a silicon process. It comes in a 24-terminal land grid array (LGA) package and provides high isolation and low insertion loss from 100 MHz to 30 GHz.This broadband switch requires dual-supply voltages, +3.3 V and ?3.3 V, and provides complementary metal-oxide semiconductor (CMOS)/low voltage transistor-transistor logic (LVTTL) logic-compatible control.Applications Test instrumentation Microwave radios and very small aperture terminals (VSATs) Military radios, radars, and electronic counter measures (ECMs) Broadband telecommunications systems

The ADRF6821 is a highly integrated, dual radio frequency (RF) input, zero intermediate frequency (IF)/low IF RFIC receiverwith a quadrature demodulator, digital step attenuator (DSA),IF linear amplifiers, an integrated, fractional-N phase-locked loop (PLL), and a low phase noise, multicore, voltage controlled oscillator (VCO). The RFIC is ideally suited for communication digital predistortion (DPD) systems.The high isolation 2:1 RF switch and on-chip wideband RFbalun enable the ADRF6821 to support two single-ended, 50 ? terminated RF inputs. A programmable attenuator ensures anoptimal differential RF input level to the high linearity demodulatorcore. The integrated attenuator offers an attenuation range of 15 dB with a step size of 1 dB. High linearity IF amplifiers follow the demodulator and provide an interface to the next componentin the chain, typically an analog-to-digital converter (ADC).The ADRF6821 offers two alternatives for generating thedifferential local oscillator (LO) input signal: internally viathe on-chip fractional-N synthesizer with low phase noiseVCOs or externally via a low phase noise LO signal. Theintegrated synthesizer enables continuous LO coverage from 450 MHz to 2800 MHz. The PLL reference input supports awide frequency range and includes integrated reference dividers before the phase frequency detector (PFD).When selected, the output of the internal fractional-N synthesizeris applied to a divide by 2, quadrature phase splitter. From theexternal LO path, a 2? LO signal can be used with the divide by 2,quadrature phase splitter to generate the quadrature LO inputs to the mixers.The ADRF6821 is fabricated using an advanced silicon germanium(SiGe), bipolar complementary metal oxide semiconductor(BiCMOS) process. It is available in a 56-lead, RoHS compliant,8 mm ? 8 mm LFCSP package with an exposed pad. Performanceis specified over the ?40?C to +105?C case temperature range.Applications Cellular W-CDMA/GSM/LTE DPD receivers? Microwave, point to point radios

The ADRV9029 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations.The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs.The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/ outputs (GPIOs) that provide an array of digital control options are also integrated.To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface.A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9029 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface.This device contains a fully integrated, low power digital predistortion (DPD) adaptation engine for use in power amplifier linearization. DPD enables use of high efficiency power amplifiers, reducing the power consumption of base station radios while also reducing the number of SERDES lanes necessary to interface with baseband processors.The low power crest factor reduction (CFR) engine of the ADRV9029 reduces the peak to average ratio (PAR) of the input signal, enabling higher efficiency transmit line ups while reducing the processing load on baseband processors.The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device.The ADRV9029 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9029 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).APPLICATIONS3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

The ADRV9029 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations.The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs.The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/ outputs (GPIOs) that provide an array of digital control options are also integrated.To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface.A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9029 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface.This device contains a fully integrated, low power digital predistortion (DPD) adaptation engine for use in power amplifier linearization. DPD enables use of high efficiency power amplifiers, reducing the power consumption of base station radios while also reducing the number of SERDES lanes necessary to interface with baseband processors.The low power crest factor reduction (CFR) engine of the ADRV9029 reduces the peak to average ratio (PAR) of the input signal, enabling higher efficiency transmit line ups while reducing the processing load on baseband processors.The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device.The ADRV9029 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9029 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).APPLICATIONS3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

The ADV3205 is a fully buffered crosspoint switch matrix that operates on ?5 V, making it ideal for video applications. It offers a ?3 dB signal bandwidth of 60 MHz and channel switch times of less than 60 ns with 0.1% settling. The ADV3205 has excellent crosstalk performance, and ground/power pins surround all inputs and outputs to provide extra shielding required for the most demanding applications. The differential gain and differential phase of better than 0.1% and 0.1?, respectively, along with 0.1 dB flatness out to 10 MHz, make the ADV3205 an excellent choice for many video applications.The ADV3205 includes 16 independent output buffers that can be placed into a disabled state for paralleling crosspoint outputs. The ADV3205 has a gain of +2 and operates on voltage supplies of ?5 V while consuming only 34 mA of current. Channel switching is performed via a serial digital control (which can accommodate daisy-chaining of several devices) or via a parallel control, allowing updating of an individual output without reprogramming the entire array.?The ADV3205 is packaged in a 100-lead LQFP and is available over the commercial temperature range of 0?C to 70?C.?ApplicationsCCTV surveillanceVideo routers (NTSC, PAL, S-Video, SECAM)Video conferencing

The ADXL213 is a low cost, low power, complete dual axis accelerometer with signal conditioned, duty cycle modulated outputs, all on a single monolithic IC. The ADXL213 measures acceleration with a full-scale range of ?1.2 g (typical). The ADXL213 can measure both dynamic acceleration (e.g., vibration) and static acceleration (e.g., gravity).The outputs are digital signals whose duty cycles (ratio of pulse width to period) are proportional to acceleration (30%/g). The duty cycle outputs can be directly measured by a microcontroller without an A/D converter or glue logic.Innovative design techniques are used to ensure high zero g bias stability (typically better than 0.25 mg/?C), as well as tight sensitivity stability (typically better than 50 ppm/?C).The typical noise floor is 160 ?g/?, allowing signals below 1 mg (0.06? of inclination) to be resolved in tilt sensing applications using narrow bandwidths (The user selects the bandwidth of the accelerometer usingcapacitors CX and CYM at the XFILT and YFILT pins. Bandwidths of0.5 Hz to 250 Hz may be selected to suit the application.The ADXL213 is available in a 5mm x 5mm x 2mm, 8-pad hermetic LCC package.ApplicationsAutomotive tilt alarmData projectorsNavigationPlatform stabilization/levelingAlarms and motion detectorsHigh accuracy, 2-axis tilt sensing