BUF16821 Evaluation Module USB

DS90UB928QEVM FPD-Link III Deserializer Evaluation Module

Dual Brushed DC Motor BoosterPack featuring DRV8848

The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need?for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated.In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time ?-? ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers.The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range.The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

Reverse Polarity Protection Smart Diode Controller Evaluation Module

LY550ALH Adapter Board Designed to be Plugged into a Standard DIL24 Socket

Evaluation Module for TPS61256; Tiny Boost Converter with Input Current Limit and Bypas

The HMC1082CHIP is a gallium arsenide (GaAs), monolithic microwave integrated circuit (MMIC), pseudomorphic high electron mobility transistor (pHEMT), driver amplifier that operates from 5.5 GHz to 18 GHz. The HMC1082CHIP provides a typical gain of 24 dB, 36 dBm output IP3, and 25.5 dBm of output power for 1 dB compression, requiring only 220 mA from a 5 V supply voltage. The saturated output power (PSAT) is 26 dBm with 24% power added efficiency (PAE).The HMC1082CHIP is an ideal driver amplifier for a wide range of applications including point to point radios from 5.5 GHz to 18 GHz and marine radars at 9 GHz. The HMC1082CHIP can also be used for 6 GHz to 18 GHz EW and ECM applications.APPLICATIONS Software defined radios Electronics warfare (EW) Radar applications Electronic countermeasures (ECMs)

The HMC374(E) is a general purpose broad band Low Noise Amplifier (LNA) for use in the 0.3 - 3.0 GHz frequency range. The LNA provides 15 dB of gain and a 1.5 dB noise figure from a single positive supply of +2.75 to +5.5V. The low noise figure coupled with a high P1dB (22 dBm) and high OIP3 (37 dBm) make this part ideal for cellular applications. The compact LNA design utilizes on-chip matching for repeatable gain and noise figure performance. To minimize board area the design is offered in a low cost SOT26 package that occupies only 0.118? x 0.118?.Applications Cellular/PCS/3G? WCS, MMDS & ISM? Fixed Wireless & WLAN? Private Land Mobile Radio

TPS51200 Sink Source DDR Termination Regulator