The ADMV1012 is a compact, gallium arsenide (GaAs) design, monolithic microwave integrated circuit (MMIC) double sideband (DSB) downconverter in a RoHS compliant package optimized for point to point microwave radio designs that operate in the 17.5 GHz to 24 GHz input frequency range. The ADMV1012 provides 15 dB of conversion gain with 25 dB of image rejection, and 2.5 dB noise figure. The ADMV1012 uses a radio frequency (RF) low noise amplifier (LNA) followed by an in phase/quadrature (I/Q), double balanced mixer, where a driver amplifier drives the local oscillator (LO) with a ?2 multiplier. IF1 and IF2 mixer quadrature outputs are provided, and an external 90? hybrid is required to select the required sideband.The I/Q mixer topology reduces the need for filtering of unwanted sideband. The ADMV1012 is a much smaller alternative to hybrid style DSB downconverter assemblies and eliminates the need for wire bonding by allowing the use of surface-mount manufacturing assemblies.The ADMV1012 downconverter comes in a compact, thermally enhanced, 4.9 mm ? 4.9 mm, 32-terminal LCC. The ADMV1012 operates over the ?40?C to +85?C temperature range.Applications Point to point microwave radios Radars and electronic warfare systems Instrumentation, automatic test equipment (ATE)Satellite communications

The ADMV1128 is a silicon on isolator (SOI), microwave, upconverter and downconverter optimized for 5G radio designs operating in the 24 GHz to 29.5 GHz frequency range.Both upconverters and downconverters offer two modes of frequency translation. One mode is conversion from and/or to single-ended or complex intermediate frequency (IF) signals, which then pass through an on-chip 90? IF hybrid, known as IF mode.The other mode is a direct conversion from and/or to differential baseband inphase/quadrature (I/Q) inputs and outputs, known as baseband mode. The I/Q baseband output common-mode voltage is programmable between 0 V and 1.5 V. The SPI provides fine adjustment of the quadrature phase to optimize I/Q demodulation performance.When the device is used as an image rejecting downconverter, the unwanted image term is typically rejected to 24 dBc, before calibration. The ADMV1128 offers a square law power detector to allow monitoring of the power levels at the mixer inputs of the downconverter.The RF receive input, RF transmit output, and local oscillator (LO) interface are all single-ended and matched to 50 ?. The on-chip RF switch provides the option to combine the transmit and receive RF ports together for time division duplex (TDD) applications. The serial port interface (SPI) provides adjustment of the quadrature phase to allow optimum sideband rejection. In addition, the SPI allows powering down the output envelope detector to reduce power consumption when carrier feedthrough optimization is not necessary.The ADMV1128 upconverter and downconverter is housed in a compact, thermally enhanced, 6 mm ? 6.5 mm, ball grid array (BGA) package. This BGA package enables the ability to heat sink the ADMV1128 from the top of the package for the most efficient thermal heat sinking. The ADMV1128 operates over the ?40?C to +95?C TC range.APPLICATIONS Millimeter-wave 5G applications Point to point microwave radios Radar and electronic warfare systems Instrumentation and automatic test equipment (ATE)

The ADMV4530 is a highly integrated upconverter with an in-phase/quadrature (I/Q) mixer that is ideally suited for next generation Ka band satellite communications.An integrated low phase noise, fractional-N phase-locked loop (PLL) with a voltage controlled oscillator (VCO) and internal 2? multiplier generate the necessary on-chip local oscillator (LO) signal for the I/Q mixer, eliminating the need for external frequency synthesis. The VCO uses an internal autocalibration routine that allows the PLL to select the necessary settings and locks in approximately 100 ?s.The single-ended reference input to the PLL operates up to 500 MHz and features internal reference dividers and a multiplier for added flexibility. Additionally, the phase frequency detector (PFD) comparison frequency can be up to 250 MHz for integer mode and 160 MHz for fraction-N mode.The upconverter consists of an I/Q mixer that can operate in either I/Q mode with 500 MHz of bandwidth or in IF mode up to 3 GHz of bandwidth, which allows various radio architectures and backward compatibility with legacy systems.Immediately following the I/Q mixer are stages of gain and variable attenuation. The configuration can achieve a minimum 1 dB compression point (P1dB) compression point of 19 dBm, eliminating the need for external stages of gain.A programmable 4-wire serial port interface (SPI) allows adjustment of the quadrature phase for optimum sideband suppression. In addition, the SPI allows nulling of LO feedthrough in IF mode. In I/Q mode, the LO feedthrough can be nulled by applying external dc offset to the differential baseband I/Q inputs.An IF automatic gain control (AGC) adjusts the IF variable gain amplifier (VGA) to compensate for input power variations. During normal operation, this AGC feature can be enabled or disabled via the SPI. When disabled during normal operation, the AGC feature only works on a test tone during power-down mode to track temperature variations.The ADMV4530 upconverter comes in a RoHs compliant, 6 mm ? 6 mm, 40-terminal land grid array (LGA) package. The ADMV4530 operates over the ?40?C to +85?C case temperature range.Applications Satellite communication Point to point microwave communication

The ADMV4928 is a silicon on insulator (SOI), 37.0 GHz to 43.5 GHz, mmW 5G beamformer. The RF integrated circuit (RFIC) is highly integrated and contains 16 independent transmit and receive channels. The ADMV4928 supports eight horizontal and eight vertical polarized antennas via independent RFV and RFH input/outputs.In transmit mode, both the RFV input and RFH input signals feed into separate amplifiers. Each path after the amplifiers splits into eight independent channels via the 1:8 power splitters. In receive mode, input signals pass through either the vertical or horizontal receive channels and combine via two independent 8:1 combiners to the common RFV pin or RFH pin. In either mode, each transmit and receive channel includes a vector modulator (VM) to control the phase, and two digital variable gain amplifiers (DVGAs) to control the amplitude. The VM provides a full 360? phase adjustment range in either transmit or receive mode to provide 6 bits of resolution for 5.625? phase steps. A phase step policy for the transmit and receive VM is provided to ensure optimum phase step performance. The total DVGA dynamic range in transmit mode is 34.5, which provides 6 bits of resolution that results in 0.5 dB amplitude steps and 5 bits of resolution that results in 1 dB amplitude steps. In receive mode, the total dynamic range is 28 dB, which provides 5 bits of resolution that results in 0.5 dB amplitude steps and 5 bits of resolution that results in 1 dB amplitude steps. The DVGAs provide a flat phase response across the full gain range. A gain policy for DVGA1 and DVGA2 is provided in the AN-2074 Application Note, ADMV4928 Application Note to ensure optimized performance across the attenuation range with 0.5 dB step resolution from 0 dB to 34.5 dB attenuation for transmit mode and 0.5 dB step resolution from 0 dB to 28 dB attenuation for receive mode. The transmit channels contain individual transmit power detectors to detect either modulated or continuous wave signals to calibrate for each channel gain as well as channel to channel gain mismatch. Each receive channel contains an RF power overload circuit (receive channel overload detection circuit) to prevent potential damage to the device as a result of blocker instances. The ADMV4928 RF ports can be connected directly to a patch antenna to create a dual polarization mmW 5G subarray.The ADMV4928 can be programmed using a 3-wire or 4-wire serial port interface (SPI). An integrated, on-chip low dropout (LDO) voltage regulator generates the 1.0 V supply for the SPI circuitry to reduce the number of supply domains required. Various SPI modes are available to enable fast startup and control during normal operation. The amplitude and phase for each channel can be set individually or multiple channels can be programmed simultaneously using the on-chip memory for beamforming. The on-chip memory can store up to 2048 beam positions that can be allocated for either transmit mode or receive mode for the horizontal channels and vertical channels. On-chip nonvolatile memory (NVM) is used to store the calibrated gain and phase offset coefficients and the reference values for each individual channel from the factory. These values are used to perform channel to channel or chip to chip calibration. In addition, four address pins (CHIP_ADDx) allow independent SPI control of up to 16 devices on the same serial lines. To control multiple devices via the same serial lines with the same instructions, activate broadcast mode via the external enable pin (BR_EN). Dedicated horizontal and vertical polarization load pins (LOAD_V and LOAD_H) provide the synchronization of all devices in the same array. A horizontal and vertical polarization transmit mode and receive mode control pin (TRX_H or TRX_V) is provided for fast switching between transmit mode and receive mode.The ADMV4928 comes in a compact, 239-ball, 10 mm ? 7 mm chip scale package ball grid array (CSP_BGA). The ADMV4928 operates over the ?40?C to +95?C case temperature (TC) range. This CSP_BGA package enables the ability to heatsink the ADMV4928 from the topside of the package for the most efficient thermal heatsinking and to allow flexible antenna placement on the opposite side of the printed circuit board (PCB).APPLICATIONSmmW 5G applicationBroadband communication

The ADMV7310 is a fully integrated system in package (SiP),in phase/quadrature (I/Q) upconverter that operates betweenan intermediate frequency (IF) input range of dc to 2 GHz anda radio frequency (RF) output range of 71 GHz to 76 GHz. Thedevice uses an image rejection mixer that is driven by a 6? localoscillator (LO) multiplier. The mixer RF output is followed by avariable gain amplifier (VGA) and a power amplifier (PA),providing a conversion gain of 35 dB typical. Differential I andQ mixer inputs are provided and can be driven with differentialI and Q baseband waveforms for direct conversion applications.Alternatively, the inputs can be driven using an external 90? hybridand two external 180? hybrids for single-ended applications.The ADMV7310 comes in a fully integrated, surface-mount,50-terminal, 16.00 mm ? 14.00 mm, chip array small outline nolead cavity (LGA_CAV) package. The ADMV7310 operatesover the ?40?C to +85?C temperature range.APPLICATIONS E-band communication systems High capacity wireless backhauls Test and measurement Aerospace and defense

The ADMV8818-EP is a fully monolithic microwave integrated circuit (MMIC) that features a digitally selectable frequency of operation. The device features four independently controlled high-pass filters (HPFs) and four independently controlled low-pass filters (LPFs) that span the 2 GHz to 18 GHz frequency range.The flexible architecture of the ADMV8818-EP allows the 3 dB cutoff frequency (f3dB) of the high-pass and low-pass filters to be controlled independently to generate up to 4 GHz of bandwidth. The digital logic control on each filter is 4 bits wide (16 states) and controls the on-chip reactive elements to adjust the f3dB. The typical insertion loss is 9 dB, and the wideband rejection is 35 dB, which is ideally suited for minimizing system harmonics.This tunable filter can be used as a smaller alternative to large switched filter banks and cavity tuned filters, and this device provides a dynamically adjustable solution in advanced communications applications.APPLICATIONSTest and measurement equipment Military radar, electronic warfare, and electronic countermeasures Satellite communications and space Industrial and medical equipment

The ADN4605 is a 40 ? 40 asynchronous, protocol agnostic,?digital crosspoint switch, with 40 differential PECL/CML-compatible inputs and 40 differential programmable CML outputs.The ADN4605 is optimized for NRZ signaling with data rates of up to 4.25 Gbps per port. Each port offers adjustable levels of input equalization, programmable output swing, and output preemphasis/deemphasis.The ADN4605 nonblocking switch core implements a 40 ? 40?crossbar and supports independent channel switching through serial and parallel control interfaces. The ADN4605 has low?latency and very low channel-to-channel skew.An I2C, SPI, or parallel interface is used to communicate with the device for control of connectivity and other features.The ADN4605 is assembled in a 35 mm ? 35 mm, 352 BGA?package and operates over a temperature range of ?40?C to +85?C.APPLICATIONS Digital video (HDMI, DVI, DisplayPort, 3G/HD/SD-SDI) Fiber optic network switching High-speed serial backplane routing to OC-48 with FEC XAUI, 4x Fibre Channel, Infiniband?, and GbE over backplane Data storage networks

The ADN8835 is a monolithic TEC controller with an integrated TEC controller. It has a linear power stage, a pulse-width modulation (PWM) power stage, and two zero-drift, rail-to-rail chopper amplifiers. The linear controller works with the PWM driver to control the internal power MOSFETs in an H bridge configuration. By measuring the thermal sensor feedback voltage and using the integrated operational amplifiers as a proportional integral differential (PID) compensator to condition the signal, the ADN8835 drives current through a TEC to settle the temperature of a laser diode or a passive component attached to the TEC module to the programmed target temperature.The ADN8835 supports negative temperature coefficient (NTC) thermistors as well as positive temperature coefficient (PTC) resistive temperature detectors (RTDs). The target temperature is set as an analog voltage input either from a digital-to-analog converter (DAC) or from an external resistor divider.The temperature control loop of the ADN8835 is stabilized by PID compensation utilizing the built in, zero-drift chopper amplifiers. The internal 2.50 V reference voltage provides a 1% accurate output that biases a thermistor temperature sensing bridge as well as a voltage divider network to program the maximum TEC current and voltage limits for both the heating and cooling modes. With the zero-drift chopper amplifiers, excellent long-term temperature stability is maintained via an autonomous analog temperature control loop.APPLICATIONS TEC temperature control Optical modules Optical fiber amplifiers Optical networking systems Instruments requiring TEC temperature control

The ADP1031 is a high performance, isolated micropowermanagement unit (PMU) that combines an isolated flybackdc-to-dc regulator, an inverting dc-to-dc regulator, and abuck dc-to-dc regulator, providing three isolated power rails.Additionally, the ADP1031 contains four, high speed, serialperipheral interface (SPI) isolation channels and three general-purpose isolators for channel to channel applications where lowpower dissipation and small solution size is required.Operating over an input voltage range of +4.5 V to +60 V, theADP1031 generates isolated output voltages of +6 V to +28 V(adjustable version) or+ 21 V and +24 V (fixed versions) forVOUT1, factory programmable voltages of +5.15 V, +5.0 V, or+3.3 V for VOUT2, and an adjustable output voltages of ?24 V to?5 V for VOUT3.By default, the ADP1031 flyback regulator operates at a 250 kHzswitching frequency and the buck and inverting regulators operateat 125 kHz. All three regulators are phase shifted relative to eachother to reduce electromagnetic interference (EMI). The ADP1031can be driven by an external oscillator in the range of 350 kHzto 750 kHz to ease noise filtering in sensitive applications.The digital isolators integrated in the ADP1031 use AnalogDevices, Inc., iCoupler? chip scale transformer technology,optimized for low power and low radiated emissions.The ADP1031 is available in a 9 mm ? 7 mm, 41-lead LFCSP andis rated for a ?40?C to +125?C operating junction temperaturerange.Applications Industrial automation and process control Instrumentation and data acquisition systems Data and power isolation

The ADP1032 is a high performance, isolated micropower management unit (PMU) that combines an isolated flyback and a dc-to-dc regulator providing two isolated power rails. Additionally, the ADP1032 contains four high speed serial peripheral interface (SPI) isolation channels and three general-purpose isolators for channel to channel applications where low power dissipation and small solution size is required. Operating over an input voltage range of 4.5 V to 60 V, the ADP1032 generates isolated output voltages of 6 V to 28 V (adjustable version) or 24 V (fixed version) for VOUT1, and factory programmable voltages of 5.15 V, 5.0 V, or 3.3 V for VOUT2.?By default, the ADP1032 flyback regulator operates at a 250 kHz switching frequency, and the buck regulator operates at 125 kHz.?The two regulators are phase shifted relative to each other to reduce electromagnetic interference (EMI). The ADP1032 can be driven by an external oscillator in the range of 350 kHz to 750 kHz to ease noise filtering in sensitive applications.?The digital isolators integrated in the ADP1032 use Analog Devices, Inc., iCoupler? chip scale transformer technology, optimized for low power and low radiated emissions. The ADP1032 is available in a 9 mm ? 7 mm, 41-lead LFCSP and is rated for a ?40?C to +125?C operating junction temperature range.?