Ethernet Development Tools Eval - 10/100 PHY w/EEE & WOL, 0.11u

TPS54341EVM-555 4.5- to 60-V Input 3.5-A Step-Down DC-DC Converter Evaluation Module

Demonstration circuit 2896A-B demonstrates a high power boost converter and features the LT®8551 the phase expander with internal gate drivers. The DC2896A-B employs LTC3769, a single-phase boost controller as primary controller and LT8551 as the phase expander which added four more power phases. The increased number of power sections connected to the LT8551, results in greater higher level output power without a corresponding increase in the difficulty of the design or a sacrifice of primary controller LTC3769 features. The input voltage range of DC2896A-B is from 10V to 46V and the output is 48V. The maximum input current is 12A per power section, so the maximum input current of DC2896A-B is 60A. It’s reflected to 30A of output current and output power of 1,440W at an input voltage of 24V. Correspondingly output current will drop to 14.5A and output power will to 720W at a 12V input voltage, to keep the input current at the same level of 60A. Both values will increase at higher voltages. The input current value can be increased above 60A, if heat sinks are installed, see parts list below. The switching frequency is 250kHz and at a 24V input to 48VOUT at full load, the efficiency of DC2896A-B is 98%. As the input voltage decreases, the output current should be decreased as well, to prevent saturation of the DC2896A-B inductors, the derating curve presented on Figure 3. Efficiency curves presented on Figure 4. DC2896A-B resistors R114 to R119 program the phase relationship between the power sections, by setting the Total Distinct Phase Number (TDPN). For increasing efficiency and reducing switching losses at light loads DC2896A-B supports disconnecting some power sections. This mode of operation designated as the stage shedding and it is programed by the jumper J3 STAGE SHED. Jumper JP1 programs the LT8551 SYNC pin and it allows DC2896A-B to be synchronized to an external clock. The print circuit board of DC2896A also supports two phase expander controllers, the LT8561 and LT8551, with versions DC2896A-A and DC2896A-B correspondingly. The table [1] in the electrical schematic describes differences between both versions, including controller biasing and gate drive voltages. DC2896A-B has jumper SHDN (JP2) for manually enable or disable controller. The SYNC (E19) input can be used to sync LT8551 with an external signal. There are also terminals that make it easy to monitor the control logic of the LT8551 functional. The current sense resistors RSNS1 to RSNS5 used for implementation of current mode control, monitoring and sharing current between the phases. To further increase efficiency DC2896A-B supports optional DCR sensing of inductors L1 to L5. DC2896A-B includes sense line filters and filter options for inputs to the LT8551 in accordance with data sheet recommendations. Undervoltage shutdown, switching frequency and LT8551 ILIM current limit levels can all be adjusted by resistors or resistor jumpers. DC2896A-B comes with a housekeeping circuit based on U3 controller. It reduces the power dissipation that would otherwise occur at high input voltages in regulator transistor Q21. The housekeeping circuit also stabilizes converter biasing at sudden input voltage drops. A high level of available output power without a corresponding high level of design complexity makes the LT8551 attractive for high power DC bus and battery systems in commercial, industrial and automotive settings. DC2896A-B features the LT8551EUKG in a thermally enhanced 52-pin 7mm × 8mm QFN package. The LT8551 and LTC3769 data sheets must be read in conjunction with this demo manual to properly use or modify DC2896A-B.

Evaluation Board for High-Speed Dual Op Amp in the 8-Pin SOIC Package

Demonstration circuit 965A is a single output high frequency step-down DC/DC converter featuring the low quiescent current LTC3835-1 in a 16-pin narrow SSOP package. The DC965A is programmed to generate a regulated 3.3V@5A output from a 4.5V to 36V input voltage. The LTC3835-1 is similar to the LTC3835 but has reduced functionality (it does not have PGOOD, ExtVCC or CLOCKOUT pins).

DRV8303 evaluation module for three-phase brushless DC pre-driver with dual current shunt am

ADS8505 evaluation module

The ADAU1978 incorporates four high performance, analog-to-digital converters (ADCs) with 2 V rms capable ac-coupled inputs. The ADCs use a multibit sigma-delta (?-?) architecture with continuous time front end for low EMI. An I2C/serial peripheral interface (SPI) control port is included that allows a microcontroller to adjust volume and many other parameters. The ADAU1978 uses only a single 3.3 V supply. The part internally generates the required digital DVDD supply. The low power architecture reduces the power consumption. The ADAU1978 is available in a 40-lead LFCSP package. The on-chip PLL can derive the master clock from an external clock input or frame clock (sample rate clock). When fed with the frame clock, it eliminates the need for a separate high frequency master clock in the system.Note that throughout this data sheet, multifunction pins, such as SCL/CCLK, are referred to either by the entire pin name or by a single function of the pin, for example, CCLK, when only that function is relevant. APPLICATIONS Automotive audio systems Active noise cancellation system

AM65x industrial development kit (IDK)

The ADuC7124/ADuC7126 is a fully integrated, 1 MSPS, 12-bit data acquisition systems incorporating high performance multichannel ADCs, 16-bit/32-bit MCUs, and Flash/EE memory on a single chip.The ADC consists of up to 12 single-ended inputs. An additional four inputs are available but are multiplexed with the four DAC output pins. The ADC can operate in single-ended or differential input modes. The ADC input voltage is 0 V to VREF. A low drift band gap reference, temperature sensor, and voltage comparator complete the ADC peripheral set. The DAC output range is programmable to one of three voltage ranges. The DAC outputs have an enhanced feature of being able to retain their output voltage during a watchdog or software reset sequence.The devices operate from an on-chip oscillator and a PLL generating an internal high frequency clock of 41.78 MHz. This clock is routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller core is an ARM7TDMI?, 16-bit/32-bit RISC machine, which offers up to 41 MIPS peak performance. Thirty-two kilobytes of SRAM and 126 kB of nonvolatile Flash/EE memory are provided on-chip. The ARM7TDMI core views all memory and registers as a single linear array.The ADuC7124 contains an advanced interrupt controller. The vectored interrupt controller (VIC) allows every interrupt to be assigned a priority level. It also supports nested interrupts to a maximum level of eight per IRQ and FIQ. When IRQ and FIQ interrupt sources are combined, a total of 16 nested interrupt levels are supported.On-chip factory firmware supports in-circuit download via the UART serial interface port or the I2C port, while nonintrusive emulation is also supported via the JTAG interface. These features are incorporated into a low cost QuickStart? Development System supporting this MicroConverter? family. The part contains a 16-bit PWM with six output signals. For communication purposes, the part contains 2?I2C channels that can be individually configured for Master or Slave mode. An SPI interface supporting both master and slave modes is also provided. Thirdly, 2?UART channels are provided. Each UART contains a configurable 16-bit FIFO with the receive and transmit buffers.The parts operate from 2.7 V to 3.6 V and are specified over an industrial temperature range of ?40?C to +125?C. When operating at 41.78 MHz, the power dissipation is typically 120 mW. The ADuC7124 is available in either 64-lead LFCSP or 80-lead LFQFP packages.APPLICATIONS Industrial control and automation systems Smart sensors, precision instrumentation Base station systems, optical networking Patient monitoring