The AD9577 provides a multioutput clock generator function,along with two on-chip phase-locked loop cores, PLL1 and PLL2,optimized for network clocking applications. The PLL designsare based on the Analog Devices, Inc., proven portfolio of highperformance, low jitter frequency synthesizers to maximizenetwork performance. The PLLs have I2C programmable outputfrequencies and formats. The fractional-N PLL can supportspread spectrum clocking for reduced EMI radiated peak power.Both PLLs can support frequency margining. Other applicationswith demanding phase noise and jitter requirements can benefitfrom this part.The first integer-N PLL section (PLL1) consists of a low noise phasefrequency detector (PFD), a precision charge pump (CP), a lowphase noise voltage controlled oscillator (VCO), a programmablefeedback divider, and two independently programmable outputdividers. By connecting an external crystal or applying a referenceclock to the REFCLK pin, frequencies of up to 637.5 MHz canbe synchronized to the input reference. Each output divider andfeedback divider ratio is I2C programmed for the requiredoutput rates.A second fractional-N PLL (PLL2) with a programmable modulusallows VCO frequencies that are fractional multiples of thereference frequency to be synthesized. Each output dividerand feedback divider ratio can be programmed for the requiredoutput rates, up to 637.5 MHz. This fractional-N PLL can alsooperate in integer-N mode for the lowest jitter.Up to four differential output clock signals can be configuredas either LVPECL or LVDS signaling formats. Alternatively,the outputs can be configured for up to eight CMOS outputs.Combinations of these formats are supported. No external loopfilter components are required, thus conserving valuable designtime and board space. The AD9577 is available in a 40-lead, 6 mm ?6 mm LFCSP package and can operate from a single 3.3 V supply.The operating temperature range is ?40?C to +85?C.Applications Low jitter, low phase noise multioutput clock generator for data communications applications including Ethernet, Fibre Channel, SONET, SDH, PCI-e, SATA, PTN, OTN, ADC/DAC, and digital video Spread spectrum clocking

The AD9652 is a dual, 16-bit analog-to-digital converter (ADC) with sampling speeds of up to 310 MSPS. It is designed to support demanding, high speed signal processing applications that require exceptional dynamic range over a wide input frequency range (up to 465 MHz). Its exceptional low noise floor of ?157.6 dBFS and large signal spurious-free dynamic range (SFDR) performance (exceeding 85 dBFS, typical) allows low level signals to be resolved in the presence of large signals.The dual ADC cores feature a multistage, pipelined architecture with integrated output error correction logic. A high performance on-chip buffer and internal voltage reference simplify the inter-face to external driving circuitry while preserving the exceptional performance of the ADC.The AD9652 can support input clock frequencies of up to 1.24 GHz with a 1, 2, 4, and 8 integer clock divider used to generate the ADC sample clock. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle. The 16-bit output data (with an overrange bit) from each ADC is interleaved onto a single LVDS output port along with a double data rate (DDR) clock. Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.The AD9652 is available in a 144-ball CSP_BGA and is specified over the industrial temperature range of ?40?C to +85?C. This product is protected by pending U.S. patents. PRODUCT HIGHLIGHTS Integrated dual, 16-bit, 310 MSPS ADCs. On-chip buffer simplifies ADC driver interface. Operation from a 3.3 V and 1.8 V supply and a separate digital output driver supply accommodating LVDS outputs. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 485 MHz. SYNC input allows synchronization of multiple devices. Three-wire, 3.3 V or 1.8 V SPI port for register programming and readback. APPLICATIONS Miltary radar and communications Multimode digital receivers (3G or 4G) Test and Instrumentation Smart antenna systems

The AD9653 is a quad, 16-bit, 125 MSPS analog-to-digital converter(ADC) with an on-chip sample-and-hold circuitdesigned for low cost, low power, small size, and ease of use.The product operates at a conversion rate of up to 125 MSPSand is optimized for outstanding dynamic performance and lowpower in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performanceoperation. No external reference or driver components arerequired for many applications.The ADC automatically multiplies the sample rate clock for theappropriate LVDS serial data rate. A data clock output (DCO) forcapturing data on the output and a frame clock output (FCO)for signaling a new output byte are provided. Individual-channelpower-down is supported and typically consumes less than 2 mWwhen all channels are disabled. The ADC contains several featuresdesigned to maximize flexibility and minimize system cost, such as programmable output clock and data alignment and digitaltest pattern generation. The available digital test patternsinclude built-in deterministic and pseudorandom patterns, alongwith custom user-defined test patterns entered via the serial portinterface (SPI).The AD9653 is available in a RoHS-compliant, 48-lead LFCSP.It is specified over the industrial temperature range of ?40?C to+85?C.PRODUCT HIGHLIGHTS Small Footprint. Four ADCs are contained in a small, space-saving package. Low power of 163 mW/channel at 125 MSPS with scalable power options. Pin compatible to the AD9253 14-bit quad and AD9633 12-bit quad ADC. Ease of Use. A data clock output (DCO) operates at frequencies of up to 500 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirementsAPPLICATIONS Medical ultrasound and MRI High speed imaging Quadrature radio receivers Diversity radio receivers Test equipment

The AD9670 is designed for low cost, low power, small size, andease of use for medical ultrasound applications. It contains eightchannels of a VGA with an LNA, a CW harmonic rejection I/Qdemodulator with programmable phase rotation, an antialiasingfilter, an ADC, and a digital demodulator and decimator for dataprocessing and bandwidth reduction.Each channel features a maximum gain of up to 52 dB, a fullydifferential signal path, and an active input preamplifier termination.The channel is optimized for high dynamic performance andlow power in applications where a small package size is critical.The LNA has a single-ended-to-differential gain that is selectablethrough the serial port interface (SPI). Assuming a 15 MHz noisebandwidth (NBW) and a 21.6 dB LNA gain, the LNA input SNRis 94 dB. In CW Doppler mode, each LNA output drives an I/Qdemodulator that has independently programmable phaserotation with 16 phase settings.Power-down of individual channels is supported to increasebattery life for portable applications. Standby mode allows quickpower-up for power cycling. In CW Doppler operation, theVGA, antialiasing filter, and ADC are powered down. The ADCcontains several features designed to maximize flexibility andminimize system cost, such as a programmable clock, dataalignment, and programmable digital test pattern generation.The digital test patterns include built-in fixed patterns, built-inpseudorandom patterns, and custom user-defined test patternsentered via the SPI.Applications Medical imaging/ultrasound Nondestructive testing (NDT)

The AD9671 is designed for low cost, low power, small size, andease of use for medical ultrasound applications. It contains eightchannels of a VGA with an LNA, a CW harmonic rejection I/Qdemodulator with programmable phase rotation, an AAF, anADC, and a digital demodulator and decimator for dataprocessing and bandwidth reduction.Each channel features a maximum gain of up to 52 dB, a fullydifferential signal path, and an active input preamplifier termination.The channel is optimized for high dynamic performance andlow power in applications where a small package size is critical.The LNA has a single-ended to differential gain that is selectablethrough the serial port interface (SPI). Assuming a 15 MHz noisebandwidth (NBW) and a 21.6 dB LNA gain, the LNA input SNRis 94 dB. In CW Doppler mode, each LNA output drives an I/Qdemodulator that has independently programmable phaserotation with 16 phase settings.Power-down of individual channels is supported to increasebattery life for portable applications. Standby mode allows quickpower-up for power cycling. In CW Doppler operation, theVGA, AAF, and ADC are powered down. The ADC containsseveral features designed to maximize flexibility and minimizesystem cost, such as a programmable clock, data alignment, andprogrammable digital test pattern generation. The digital testpatterns include built-in fixed patterns, built-in pseudorandompatterns, and custom user defined test patterns entered via the SPI.Applications Medical imaging/ultrasound Nondestructive testing (NDT)

The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40?C to +85?C industrial temperature range. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm ? 9 mm, 64-lead LFCSP.APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD9681 is an octal, 14-bit, 125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. The device operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and an LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.The AD9681 automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. Data clock outputs (DCO?1, DCO?2) for capturing data on the output and frame clock outputs (FCO?1, FCO?2) for signaling a new output byte are provided. Individual channel power-down is supported, and the device typically consumes less than 2 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).The AD9681 is available in an RoHS-compliant, 144-ball CSP-BGA. It is specified over the industrial temperature range of ?40?C to +85?C. This product is protected by a U.S. patent.Product Highlights Small Footprint. Eight ADCs are contained in a small, 10 mm ? 10 mm package. Low Power. The device dissipates 110 mW per channel at 125 MSPS with scalable power options. Ease of Use. Data clock outputs (DCO?1, DCO?2) operate at frequencies of up to 500 MHz and support double data rate (DDR) operation. User Flexibility. SPI control offers a wide range of flexible features to meet specific system requirements. Application Medical imaging Communications receivers Multichannel data acquisition

The AD9695 is a dual, 14-bit, 1300 MSPS/625 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 2 GHz. The ?3 dB bandwidth of the ADC input is 2 GHz. The AD9695 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of multiple signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and decimation filters. The NCO has the option to select up to 16 preset bands over the general-purpose input/output (GPIO) pins, or use a coherent fast frequency hopping mechanism for band selection. Operation of the AD9695 between the DDC modes is selectable via SPI-programmable profiles.In addition to the DDC blocks, the AD9695 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9695 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.The user can configure the Subclasss 1 JESD204B-based high speed serialized output using either one lane, two lanes, or four lanes, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9695 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire serial port interface (SPI) and or PDWN/STBY pin.The AD9695 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40?C to +105?C junction temperature range. This product may be protected by one or more U.S. or international patents.Note that, throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant.Product Highlights Low power consumption per channel. JESD204B lane rate support up to 16 Gbps. Wide, full power bandwidth supports intermediate frequency (IF) sampling of signals up to 2 GHz. Buffered inputs ease filter design and implementation. Four integrated wideband decimation filters and NCO blocks supporting multiband receivers. Programmable fast overrange detection. On-chip temperature diode for system thermal management.Applications Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, WCDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receiver Instrumentation Oscilloscopes Spectrum analyzers Network analyzers Integrated RF test solutions Radars Electronic support measures, electronic counter measures, and electronic counter-counter measures High speed data acquisition systems DOCSIS 3.0 CMTS upstream receive paths Hybrid fiber coaxial digital reverse path receivers Wideband digital predistortion

The AD9704/AD9705/AD9706/AD9707 are the fourth-generation family in the TxDAC series of high performance, CMOS digital-to-analog converters (DACs). This pin-compatible, 8-/10-/12-/14-bit resolution family is optimized for low power operation, while maintaining excellent dynamic performance. The AD9704/AD9705/AD9706/AD9707 family is pin-compatible with the AD9748/AD9740/AD9742/AD9744 family of TxDAC converters and is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface, LFCSP package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9704/AD9705/AD9706/AD9707 offers exceptional ac and dc performance, while supporting update rates up to 175 MSPS.The flexible power supply operating range of 1.7 V to 3.6 V and low power dissipation of the AD9704/AD9705/AD9706/AD9707 parts make them well suited for portable and low power applications.Power dissipation of the AD9704/AD9705/AD9706/AD9707 can be reduced to 15 mW, with a small trade-off in performance, by lowering the full-scale current output. In addition, a power-down mode reduces the standby power dissipation to approximately 2.2 mW.The AD9704/AD9705/AD9706/AD9707 has an optional serial peripheral interface (SPI?) that provides a higher level of programmability to enhance performance of the DAC. An adjustable output, common-mode feature allows for easy interfacing to other components that require common modes from 0 V to 1.2 V.Edge-triggered input latches and a 1.0 V temperature-compensated band gap reference have been integrated to provide a complete, monolithic DAC solution. The digital inputs support 1.8 V and 3.3 V CMOS logic families.PRODUCT HIGHLIGHTS Pin Compatible. The AD9704/AD9705/AD9706/AD9707 line of TxDAC?converters is pin-compatible with theAD9748/AD9740/AD9742/AD9744 TxDAC line (LFCSP package). Low Power. Complete CMOS DAC operates on a single supply of 3.6 V down to 1.7 V, consuming 50 mW (3.3 V) and 12 mW (1.8 V). The DAC full-scale current can be reduced for lower power operation. Sleep and power-down modes are provided for low power idle periods. Self-Calibration. Self-calibration enables true 14-bit INL and DNL performance in the AD9707. Twos Complement/Binary Data Coding Support. Data input supports twos complement or straight binary data coding. Flexible Clock Input. A selectable high speed, single-ended,and differential CMOS clock input supports 175 MSPS conversion rate. Device Configuration. Device can be configured through pin strapping, and SPI control offers a higher level of programmability. Easy Interfacing to Other Components. Adjustable common-mode output allows for easy interfacing to other signal chain components that accept common-mode levels from 0 V to 1.2 V. On-Chip Voltage Reference. The AD9704/AD9705/AD9706/AD9707 include a 1.0 V temperature-compensated band gap voltage reference. Industry-Standard 32-Lead LFCSP Package.

The AD9740 is a 10-bit resolution, wideband, third generation member of the TxDAC series of high performance, low power CMOS digital-to-analog converters (DACs). The TxDAC family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface options, small outline package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9740 offers exceptional ac and dc performance while supporting update rates up to 210 MSPS. The AD9740?s low power dissipation makes it well suited for portable and low power applications. Its power dissipation can be further reduced to 60 mW with a slight degradation in performance by lowering the full-scale current output. In addition, a power-down mode reduces the standby power dissipation to approximately 15 mW. A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Edge-triggered input latches and a 1.2 V temperature-compensated band gap reference have been integrated to provide a complete monolithic DAC solution. The digital inputs support 3 V CMOS logic families. PRODUCT HIGHLIGHTS The AD9740 is the 10-bit member of the pin-compatible TxDAC family, which offers excellent INL and DNL performance. Data input supports twos complement or straight binary data coding. High speed, single-ended CMOS clock input supports 210 MSPS conversion rate. Low power: Complete CMOS DAC function operates on 135 mW from a 2.7 V to 3.6 V single supply. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for low power idle periods. On-chip voltage reference: The AD9740 includes a 1.2 V temperature-compensated band gap voltage reference. Industry-standard 28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP packages.?APPLICATIONSWideband communication transmit channel Direct IF Base stations Wireless local loops Digital radio links Direct digital synthesis (DDS) Instrumentation