The HMC1010LP4E Power Detector is designed for RF power measurement, and control applications for frequencies up to 3.9 GHz. The detector provides an accurate RMS representation of any RF/IF input signal. The output is a temperature compensated monotonic, representation of real signal power, measured with an input sensing range of 60 dB.The HMC1010LP4E is ideally suited to those wide bandwidth, wide dynamic range applications, requiring repeatable measurement of real signal power, especially where RF/IF wave shape and/or crest factor change with time.The integration bandwidth of the HMC1010LP4E is digitally programmable with the use of input pins SC I1- 4 with a range of more than 4 decades. This allows the user to dynamically set the operation bandwidth providing the capability of handling different types of modulations on the same platform.The HMC1010LP4E features an internal op-amp at output stage, which provides for slope & intercept adjustments and enables controller application.Applications Log ?> Root-Mean-Square?(RMS) Conversion Received Signal Strength?Indication (RSSI) Transmitter Signal Strength?Indication (TSSI) RF Power Amplifier Efficiency Control Receiver Automatic Gain Control Transmitter Power Control

The HMC1021LP4E is an RMS power detector with an integrated high bandwidth envelope detector. The RMS output is a temperature compensated, monotonic, linear-in-dB representation of real RF signal power, measured over an input sensing range of 70 dB.The envelope detector provides an accurate voltage output which is linearly proportional to the envelope amplitude of the RF input signal for modulation bandwidths up to 150 MHz. The high bandwidth envelope detection of the HMC1021LP4E makes it ideal for detecting broadband and high crest factor RF signals commonly used in CDMA2000, WCDMA, and LTE systems. Additionally, the instantaneous envelope output can be used to create fast, excessive RF power protection, PA linearization, and efficiency enhancing envelopetracking PA implementations.The HMC1021LP4E?s RMS detector integration bandwidth is digitally programmable via input pins SCI1-4 over a range of more than 4 decades. This allows the user to dynamically set the operation bandwidth and also permits the detection of different types of modulations on the same platform.The HMC1021LP4E features an internal op-amp at the RMS output stage, which accommodates slope and intercept adjustments and supports a wide range of applications.Applications Log ?> Root-Mean-Square (RMS) Conversion Tx/Rx Signal Strength Indication (TSSI / RSSI) RF Power Amplifier Efficiency Control Receiver Automatic Gain Control Transmitter Power Control Envelope Tracking PA Linearization

The HMC948LP3E Logarithmic Detector converts RF signals at its input, to a proportional DC voltage at its output. The HMC948LP3E employs successive compression topology which delivers high dynamic range over a wide input frequency range. As the input power is increased, successive amplifiers move into saturation one by one creating an approximation of the logarithm function.The output of a series of square law detectors is summed, converted into the voltage domain and buffered to drive the LOG OUT output. The HMC948LP3E provides a nominal logarithmic slope of +14.2 mV/dB and an intercept of -111 dBm at 23 GHz. Ideal as a log detector for high volume microwave radio and VSAT applications, the HMC948LP3E is housed in a compact 3x3 mm RoHS compliant SMT plastic package.Applications Point-to-Point Microwave Radio VSAT Wideband Power Monitoring Receiver Signal Strength?Indication (RSSI) Test & Measurement

The AD6674 is a 385 MHz bandwidth mixed-signal intermediate frequency (IF) receiver. It consists of two, 14-bit 1.0 GSPS/750 MSPS/500 MSPS analog-to-digital converters (ADC) and various digital signal processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. It has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of sampling wide bandwidth analog signals of up to 2 GHz. The AD6674 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.Applications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD6674 is a 385 MHz bandwidth mixed-signal intermediate frequency (IF) receiver. It consists of two, 14-bit 1.0 GSPS/750 MSPS/500 MSPS analog-to-digital converters (ADC) and various digital signal processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. It has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of sampling wide bandwidth analog signals of up to 2 GHz. The AD6674 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.Applications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD6674 is a 385 MHz bandwidth mixed-signal intermediate frequency (IF) receiver. It consists of two, 14-bit 1.0 GSPS/750 MSPS/500 MSPS analog-to-digital converters (ADC) and various digital signal processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. It has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of sampling wide bandwidth analog signals of up to 2 GHz. The AD6674 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.Applications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD724 is a low cost RGB to NTSC/PAL Encoder that converts red, green and blue color component signals into their corresponding luminance (baseband amplitude) and chrominance (subcarrier amplitude and phase) signals in accordance with either NTSC or PAL standards. These two outputs are also combined to provide composite video output. All three outputs can simultaneously drive 75 (ohm), reverse-terminated cables. All logical inputs are CMOS compatible. The chip operates from a single +5 V supply. No external delay lines or filters are required. The AD724 may be powered down when not in use.The AD724 accepts either FSC or 4FSC clock. When a clock is not available, a low cost parallel-resonant crystal (3.58 MHz (NTSC) or 4.43 MHz (PAL)) and the AD724?s on-chip oscilla-tor generate the necessary subcarrier clock. The AD724 also accepts the subcarrier clock from an external video source.The interface to graphics controllers is simple: an on-chip logic ?XNOR? accepts the available vertical (VSYNC) and horizontal sync (HSYNC) signals and creates the composite sync (CSYNC) signal on-chip. If available, the AD724 will also accept a standard CSYNC signal by connecting VSYNC to +5 V and applying CSYNC to the HSYNC pin. The AD724 contains decoding logic to identify valid horizontal sync pulses for correct burst insertion.Delays in the U and V chroma filters are matched by an on-chip sampled-data delay line in the Y signal path. To prevent aliasing, a prefilter at 5 MHz is included ahead of the delay line and a post-filter at 5 MHz is added after the delay line to suppress harmonics in the output. These low-pass filters are optimized for minimum pulse overshoot. The overall luma delay, relative to chroma, has been designed to be time aligned for direct input to a television?s baseband. The AD724 comes in a space-saving SOIC and is specified for the 0?C to +70?C commercial temperature range.An evaluation board is available for this product and may be ordered using the following product number: AD724-EB.

The AD8013 is a low power, single supply, triple video amplifier. Each of the three amplifiers has 30 mA of output current, and is optimized for driving one back terminated video load (150 ?) each. Each amplifier is a current feedback amp-lifier and features gain flatness of 0.1 dB to 60 MHz while offering differential gain and phase error of 0.02% and 0.06? This makes the AD8013 ideal for broadcast and professional video electronics.The AD8013 offers low power of 4 mA per amplifier max and runs on a single +5 V to +13 V power supply. The outputs of each amplifier swing to within one volt of either supply rail to easily accommodate video signals. The AD8013 is unique among current feedback op amps by virtue of its large capacitive load drive. Each op amp is capable of driving large capacitive loads while still achieving rapid settling time. For instance it can settle in 18 ns driving a resistive load, and achieves 40 ns (0.1%) settling while driving 200 pF.The outstanding bandwidth of 150 MHz along with 1000 V/?s of slew rate make the AD8013 useful in many general purpose high speed applications where a single +5 V or dual power supplies up to ?6.5 V are required. Furthermore the AD8013's high speed disable function can be used to power down the amplifier or to put the output in a high impedance state. This can then be used in video multiplexing applications. The AD8013 is available in the industrial temperature range of -40?C to +85?C.

The AD8074 /AD8075 are high-speed triple video buffers with a G = +1 and +2 respectively. They operate on ?5V and have a -3dB full signal bandwidth in excess of 500MHz, along with slew rates in excess of 1350V/?s. With better than -80dB of all hostile crosstalk and 90dB isolation, they are useful in many high-speed applications. The differential gain and differential phase error are 0.01% and 0.01?. Gain Flatness of 0.1dB up to 70MHz make the AD8074/75 ideal for RGB buffering or driving. They consume less than 30mA on a ?5V supply voltage.Both devices offer a high-speed disable feature that allows the outputs to be put into a high impedance state. This allows the building of larger input arrays while minimizing 'OFF' channel output loading. The AD8074/75 are offered in a 16 lead TSSOP package.

The AD8113 is a fully buffered crosspoint switch matrix that operates on ?12V for Audio applications and ?5V for Video applications. It offers a -3dB signal bandwidth greater than 60MHz and channel switch times of less than 60ns with 0.1% settling for use in both analog and digital audio. The AD8113 operated at 20kHz has crosstalk performance of -83dB and isolation of 90dB. In addition, ground/power pins surround all inputs and outputs to provide extra shielding for operation in the most demanding audio routing applications. The differential gain and differential phase of better than 0.1% and 0.1?, respectively, along with 0.1dB flatness out to 10MHz make the AD8113 suitable for many video applications.The AD8113 includes 16 independent output buffers that can be placed into a disabled state for paralleling crosspoint outputs so that off channel loading is minimized. The AD8113 has a gain of +2. It operates on voltage supplies of ?5V or ?12V while consuming only 34mA or 31mA of current, respectively.The channel switching is performed via a serial digital control (which can accommodate daisy-chaining of several devices) or via a parallel control, allowing updating of an individual output without reprogramming the entire array.The AD8113 is packaged in a 100-lead LQFP and is available over the commercial temperature range of 0?C to 70?C.