Demonstration circuit 1586A is a high efficiency, dual-output (3.3V and 2.5V), synchronous buck converter with 4.5V to 25V input range. It can supply 5A maximum load current at 3.3V and 2.5V outputs. The demo board uses the LTC3855EUJ controller. The LTC3855 is a feature-rich dual-output dual-phase synchronous buck controller with on-chip drivers, remote output voltage sensing (VOUT2) and inductor DCR temperature compensation.

The LT3574 is a monolithic switching regulator specifically designed for the isolated flyback topology. No third winding or opto-isolator is required for regulation. The part senses the isolated output voltage directly from the primary side flyback waveform. A 0.65A, 60V NPN power switch is integrated along with all control logic into a 16?lead MSOP package. The LT3574 operates with input supply voltages from 3V to 40V, and can deliver output power up to 3W with no external power switch. The LT3574 utilizes boundary mode operation to provide a small magnetic solution with improved load regulation. The output voltage is easily set with two external resistors and the transformer turns ratio. Off-the-shelf transformers are available for many applications.Applications Industrial, Automotive and Medical Isolated Power Supplies

The LTC2328-18 is a low noise, high speed 18-bit successive approximation register (SAR) ADC with pseudo-differential inputs. Operating from a single 5V supply, the LTC2328-18 has a ?10.24V true bipolar input range, making it ideal for high voltage applications which require a wide dynamic range. The LTC2328-18 achieves ?5LSB INL maximum, no missing codes at 18 bits with 95dB SNR.The LTC2328-18 has an onboard single-shot capable reference buffer and low drift (20ppm/?C max) 2.048V temperature compensated reference. The LTC2328-18 also has a high speed SPI-compatible serial interface that supports 1.8V, 2.5V, 3.3V and 5V logic while also featuring a daisy-chain mode. The fast 1Msps throughput with no cycle latency makes the LTC2328-18 ideally suited for a wide variety of high speed applications. An internal oscillator sets the conversion time, easing external timing considerations. The LTC2328-18 dissipates only 50mW and automatically naps between conversions, leading to reduced power dissipation that scales with the sampling rate. A sleep mode is also provided to reduce the power consumption of the LTC2328-18 to 300?W for further power savings during inactive periods. Bits LTC2328-16 16 LTC2328-18 18 Applications Programmable Logic Controllers Industrial Process Control High Speed Data Acquisition Portable or Compact Instrumentation ATE

Demonstration circuit 2069A features LT8490, a high performance buck-boost converter that implements an MPPT function and flexible charging profiles suitable for most battery types such as flooded and sealed lead acid batteries and Lithium-Ion batteries, and can operate from input voltages above, below or equal to the battery voltage.

Demonstration circuit 2234A is a synchronous sepic converter featuring the LT8711 multitopology switching controller. The LT8711 is a current mode PWM DC/DC controller with a dual input LDO to optimize gate driver efficiency. Ultralow 15μA quiescent current in low noise Burst Mode® operation achieves high efficiency at very light loads and helps extend the run-time in battery powered applications when in standby mode. The LT8711 switching frequency can be programmed either via oscillator resistor or external clock over a 100kHz to 750kHz range.

The AD9148 is a quad, 16-bit, high dynamic range, digital-toanalogconverter (DAC) that provides a sample rate of 1000 MSPS.These devices include features optimized for direct conversiontransmit applications, including gain, phase, and offset compensation.The DAC outputs are optimized to interface seamlessly withanalog quadrature modulators such as the?ADL5371/ADL5372/ADL5373/ADL5374/ADL5375/. A serial peripheral interface (SPI)is provided for programming of the internal device parameters.Full-scale output current can be programmed over a range of 10 mAto 30 mA. The devices operate from 1.8 V and 3.3 V supplies fora total power consumption of 3 W at the maximum sample rate.They are enclosed in 196-ball chip scale package ball grid arraywith the option of an attached heat spreader..Product Highlights1. Low noise and inter-modulation distortion (IMD) enable highquality synthesis of wideband signals from baseband to highintermediate frequencies.2. A proprietary DAC output switching technique enhancesdynamic performance.3. The current outputs are easily configured for various singleendedor differential circuit topologies.4. LVDS data input interface includes FIFO to ease input timing.Applications Wireless infrastructure LTE, TD-SCDMA, WiMAX, WCDMA, CDMA2000, GSM MIMO/Transmit diversity Digital high or low IF synthesis

The AD9213 is a single, 12-bit, 6 GSPS/10.25 GSPS, radio frequency (RF) analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. The AD9213 supports high dynamic range frequency and time domain applications requiring wide instantaneous bandwidth and low conversion error rates (CER). The AD9213 features a 16-lane JESD204B interface to support maximum bandwidth capability.The AD9213 achieves dynamic range and linearity performance while consuming <4.6 W typical. The device is based on an interleaved pipeline architecture and features a proprietary calibration and randomization technique that suppresses interleaving spurious artifacts into its noise floor. The linearity performance of the AD9213 is preserved by a combination of on-chip dithering and calibration, which results in excellent spurious-free performance over a wide range of input signal conditions.?Applications that require less instantaneous bandwidth can benefit from the on-chip, digital signal processing (DSP) capability of the AD9213 that reduces the output data rate along with the number of JESD204B lanes required to support the device. The DSP path includes a digital downconverter (DDC) with a 48-bit, numerically controlled oscillator (NCO), followed by an I/Q digital decimator stage that allows selectable decimation rates that are factors of two or three. For fast frequency hopping applications, the AD9213 NCO supports up to 16 profile settings with a separate trigger input, allowing wide surveillance frequency coverage at a reduced JESD204B lane count.The AD9213 supports sample accurate multichip synchronization that includes synchronization of the NCOs. The AD9213 is offered in a 192-ball ball grid array (BGA) package and is specified over a junction temperature range of ?20?C to +115?C.

The AD9213 is a single, 12-bit, 6 GSPS/10.25 GSPS, radio frequency (RF) analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. The AD9213 supports high dynamic range frequency and time domain applications requiring wide instantaneous bandwidth and low conversion error rates (CER). The AD9213 features a 16-lane JESD204B interface to support maximum bandwidth capability.The AD9213 achieves dynamic range and linearity performance while consuming <4.6 W typical. The device is based on an interleaved pipeline architecture and features a proprietary calibration and randomization technique that suppresses interleaving spurious artifacts into its noise floor. The linearity performance of the AD9213 is preserved by a combination of on-chip dithering and calibration, which results in excellent spurious-free performance over a wide range of input signal conditions.?Applications that require less instantaneous bandwidth can benefit from the on-chip, digital signal processing (DSP) capability of the AD9213 that reduces the output data rate along with the number of JESD204B lanes required to support the device. The DSP path includes a digital downconverter (DDC) with a 48-bit, numerically controlled oscillator (NCO), followed by an I/Q digital decimator stage that allows selectable decimation rates that are factors of two or three. For fast frequency hopping applications, the AD9213 NCO supports up to 16 profile settings with a separate trigger input, allowing wide surveillance frequency coverage at a reduced JESD204B lane count.The AD9213 supports sample accurate multichip synchronization that includes synchronization of the NCOs. The AD9213 is offered in a 192-ball ball grid array (BGA) package and is specified over a junction temperature range of ?20?C to +115?C.

The AD9217 is a single, 12-bit, 6 GSPS/10.25 GSPS, radio frequency (RF) analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. The AD9217 supports high dynamic range frequency and time domain applications requiring wide instantaneous bandwidth and low conversion error rates (CER).The AD9217 features a low latency, high speed, parallel CML output interface that supports full bandwidth operation with compatible FPGA/ASIC receivers. The AD9217 can be reconfigured to operate in native AD9213 mode for applications requiring additional digital processing and JESD204B output support. Refer to the AD9213 data sheet?when operating the AD9217 in AD9213 mode.The AD9217 achieves dynamic range and linearity performance while consuming 4.2 W typical. The device is based on an interleaved pipeline architecture and features a proprietary calibration and randomization technique that suppresses interleaving spurious artifacts into its noise floor. The linearity performance of the AD9217 is preserved by a combination of on-chip dithering and calibration, which results in excellent spurious-free performance over a wide range of input signal conditions.The AD9217 is offered in a 192-ball ball grid array (BGA) package and is specified over a junction temperature range of ?20?C to +115?C.

The AD9986 is a highly integrated device with a 16-bit, 12 GSPS maximum sample rate RF DAC core, and a 12-bit, 6 GSPS rate RF ADC core. The AD9986 supports four transmitter channels and two receiver channels with four transmitter, two receiver (4T2R) configuration. The AD9986 is well suited for 2-antenna and 4-antenna transmitter applications requiring a wide bandwidth observation receiver path for the digital predistortion. The AD9986 supports up to a 6 GSPS complex transmit and receive data rate in single channel mode. The maximum radio channel bandwidth supported is 1.2 GHz and 2.4 GHz for the transmit and receive paths, respectively (4T2R). The AD9986 features a 16 lane, 24.75 Gbps JESD204C or 15.5 Gbps JESD204B serial data port, an on-chip clock multiplier, and digital signal processing capability targeted at multiband, direct-to-RF radio applications. APPLICATIONS Wireless communications infrastructure W-CDMA, LTE, LTE-A, Massive-MIMO Microwave point-to-point, E-band, and 5G mm Wave Broadband communications systems DOCSIS 3.1 and 4.0 CMTS Communications test and measurement system