RF Development Tools RF MOSFET (VDMOS)

Bluetooth Development Tools (802.15.1) Module Kit

The ADAL6110-16 is a light detection and ranging (LIDAR)signal processor IC that supports simultaneous capture of up to16 channels. Each channel is integrated with a 16-bit analog todigital converter (ADC) to measure the optical return signal.The ADAL6110-16 stores the captured waveforms to staticrandom access memory (SRAM) storage. The data outputreadout and functional configuration of the LIDAR signalprocessor occurs over a 4-wire serial port interface (SPI).The LIDAR signal processor features a dc balance control toreject signal offset and corruption due to modulated interference,eliminating the need for external dc cancellation circuitry. Inaddition, the LIDAR signal processor has a built-in automaticgain control (AGC) that modifies the gain of the system toensure the signal of interest is automatically scaled to themeasurement range.The ADAL6110-16 simplifies the traditional multichannelLIDAR system implementation by integrating the transimpedanceamplifier (TIA), gain and sampling stages, as well as providingthe transmitter fire signal, all of which are managed by on-chipcontrol logic. No external components are required between thephotodiodes and the TIA interface of each channel in theLIDAR signal processor.Applications Autonomous systems collision avoidance Corridor mapping Dynamic suspension and flight control Drone altitude monitoring Industrial distance measurement Mounted safety curtain systems Parking spot monitoring Blind spot detection

The ADRV9026 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations. The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs. The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) that provide an array of digital control options are also integrated. To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface. A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9026 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface. The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device. The ADRV9026 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9026 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

Optical Sensor Development Tools TMG4903 EVM Rev. 2.0

Digital to Analog Converters - DAC CMOS CONVERTER IC

6V, DUAL 2A/2A OR 3A/1A,LOW QUIESCENT CURRENT,SYNCHRONOUS BUCK WITH PG AND SSEVALUATION BOARD

HIGH-EFFICIENCY, FAST-TRANSIENT, 3.5A, 36VSTEP-DOWN CONVERTER EVALUATION BOARD

1A, 60V, HIGH-EFFICIENCY, SYNCHRONOUSSTEP-DOWN CONVERTEREVALUATION BOARD

2A, 60V, HIGH-EFFICIENCY, SYNCHRONOUSSTEP-DOWN CONVERTEREVALUATION BOARD