The ADAU7002 converts a stereo PDM bit stream into a PCMoutput. The source for the PDM data can be two microphonesor other PDM sources. The PCM audio data is output on aserial audio interface port in either I2S or TDM format.The ADAU7002 is specified over the commercial temperaturerange (?40?C to +85?C). It is available in a halide-free, 8-ball,1.56 mm ? 0.76 mm, wafer level chip scale package (WLCSP).Applications Mobile computing Portable electronics Consumer electronics

The ADE9430 is a highly accurate, fully integrated, polyphase energy and power quality monitoring device. Superior analog performance and a digital signal processing (DSP) core enable accurate energy monitoring over a wide dynamic range. An integrated high end reference ensures low drift over temperature with a combined drift of less than ?25 ppm/?C maximum for the entire channel including a programmable gain amplifier (PGA) and an analog-to-digital converter (ADC).The ADE9430 offers a complete power quality monitoring capability by providing instantaneous total as well as fundamental measurements on rms, frequency, phase angle, power factor active, reactive, and apparent powers and energies. Using the optional ADSWPQ-CLS Power Quality Library, advanced power quality features, such as dip and swell monitoring, power frequency, voltage total harmonic distortion (VTHD), and current total harmonic distortion (ITHD), are enabled. The one cycle rms, 10 cycle rms/12 cycle rms, and the optional ADSW-PQ-CLS Power Quality Library features are calculated according to IEC 61000-4-30 Class S. To request access to the ADSW-PQ-CLS, fill out the software request form at: Software Request Form | Analog Devices, where the target technology must be power quality monitoring and the processor/system on chip (SoC) is the ADE9430.The ADE9430 offers a resampled waveform of 1024 points per 10 cycles or 12 cycles. Resampling simplifies the fast Fourier transform (FFT) calculation of at least 40 harmonics in an external processor.The ADE9430 simplifies the implementation and certification of energy and power quality monitoring systems by providing tight integration of acquisition and calculation engines. The integrated ADCs and DSP engine calculate various parameters and provide data through user accessible registers or indicate events through interrupt pins. With seven dedicated ADC channels, the ADE9430 can be used on a 3-phase system or up to three single-phase systems. This device supports current transformers (CTs) or Rogowski coils when used with external analog integrator for current measurements.The ADE9430 absorbs most of the complexity in calculations for a power quality monitoring system. Combining a simple host microcontroller and the optional ADSW-PQ-CLS Power Quality Library, the ADE9430 enables the design of standalone monitoring or protection systems, or low cost nodes uploading data into the cloud.APPLICATIONS Energy and power monitoring Standards compliant power quality monitoring Protective devices Machine health Smart power distribution units Polyphase energy meters

The ADF7021 is a low power, highly integrated 2FSK/3FSK/4FSK transceiver. It is designed to operate in the narrowband, license-free ISM bands and licensed bands in the 80 MHz to 650 MHz and 862 MHz to 940 MHz frequency ranges. It has both Gaussian and raised cosine data filtering options to improve spectral efficiency for narrowband applications.It is suitable for circuit applications targeted at European ETSI-EN 300-220, the Japanese ARIB STD-T67, the Chinese Short Range Device regulations, and the North American FCC Part 15, Part 90, and Part 95 regulatory standards. A complete transceiver can be built using a small number of external discrete components, making the ADF7021 very suitable for price-sensitive and area-sensitive applications.The transmit section contains a voltage controlled oscillator (VCO) and a low noise fractional-N PLL with output resolution of <1 ppm. This frequency-agile PLL allows the ADF7021 to be used in frequency hopping spread spectrum (FHSS) systems. The VCO operates at twice the fundamental frequency to reduce spurious emissions and frequency pulling problems. The transmitter output power is programmable in 63 steps from ?16 dBm to +13 dBm and has an automatic power ramp control to prevent spectral splatter and help meet regulatory standards. The transceiver RF frequency, channel spacing, and modulation are programmable using a simple 3-wire interface. The device operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use.A low IF architecture is used in the receiver (100 kHz), minimizing power consumption and the external component count while avoiding interference problems at low frequencies. The IF filter has programmable bandwidths of 12.5 kHz, 18.75 kHz, and 25 kHz. The ADF7021 supports a wide variety of programmable features including Rx linearity, sensitivity, and IF bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. The receiver also features a patent-pending automatic frequency control (AFC) loop with programmable pull-in range, allowing the PLL to track out the frequency error in the incoming signal.An on-chip ADC provides readback of an integrated temperature sensor, an external analog input, the battery voltage, and the RSSI signal, which provides savings on an ADC in some applications. The temperature sensor is accurate to ?10?C over the full operating temperature range of ?40?C to +85?C. This accuracy can be improved by doing a 1-point calibration at room temperature and storing the result in memory.

The ADRV9026 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations. The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs. The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) that provide an array of digital control options are also integrated. To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface. A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9026 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface. The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device. The ADRV9026 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9026 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

DC1080A: Demo Board for the LTC4268-1 High Power PD with Synchronous No Opto Flyback Controller.

DC1082A-B: Demo Board for the LTC1407A Serial 14-Bit, 3Msps Simultaneous Sampling ADCs with Shutdown.

Demonstration circuit 1586A is a high efficiency, dual-output (3.3V and 2.5V), synchronous buck converter with 4.5V to 25V input range. It can supply 5A maximum load current at 3.3V and 2.5V outputs. The demo board uses the LTC3855EUJ controller. The LTC3855 is a feature-rich dual-output dual-phase synchronous buck controller with on-chip drivers, remote output voltage sensing (VOUT2) and inductor DCR temperature compensation.

The LT3574 is a monolithic switching regulator specifically designed for the isolated flyback topology. No third winding or opto-isolator is required for regulation. The part senses the isolated output voltage directly from the primary side flyback waveform. A 0.65A, 60V NPN power switch is integrated along with all control logic into a 16?lead MSOP package. The LT3574 operates with input supply voltages from 3V to 40V, and can deliver output power up to 3W with no external power switch. The LT3574 utilizes boundary mode operation to provide a small magnetic solution with improved load regulation. The output voltage is easily set with two external resistors and the transformer turns ratio. Off-the-shelf transformers are available for many applications.Applications Industrial, Automotive and Medical Isolated Power Supplies

The LTC3861 is a dual PolyPhase? synchronous stepdown switching regulator controller for high current distributed power systems, digital signal processors, and other telecom and industrial DC/DC power supplies. It uses a constant-frequency voltage mode architecture combined with very low offset, high bandwidth error amplifiers and a remote output sense differential amplifier per channel for excellent transient response and output regulation.The controller incorporates lossless inductor DCR current sensing to maintain current balance between phases and to provide overcurrent protection. The chip operates from a VCC supply between 3V and 5.5V and is designed for stepdown conversion from VIN between 3V and 24V to output voltages between 0.6V and VCC ? 0.5V.The TRACK/SS pins provide programmable soft-start or tracking functions. Inductor current reversal is disabled during soft-start to safely power prebiased loads. The constant operating frequency can be synchronized to an external clock or linearly programmed from 250kHz to 2.25MHz. Up to six LTC3861 controllers can operate in parallel for 1-, 2-, 3-, 4-, 6- or 12-phase operation.The LTC3861 is available in a 36-pin 5mm ? 6mm QFN package. LTC3861-1 is a 32-pin QFN version of the LTC3861, which has a single differential remote output voltage sense amplifier. # Diff Amps Config Pin Package LTC3861 2 Yes 5 x 6 QFN-36 LTC3861-1 1 No 5 x 5 QFN-32 Applications High Current Distributed Power Systems DSP, FPGA and ASIC Supplies Datacom and Telecom Systems Industrial Power Supplies

The LTC2328-18 is a low noise, high speed 18-bit successive approximation register (SAR) ADC with pseudo-differential inputs. Operating from a single 5V supply, the LTC2328-18 has a ?10.24V true bipolar input range, making it ideal for high voltage applications which require a wide dynamic range. The LTC2328-18 achieves ?5LSB INL maximum, no missing codes at 18 bits with 95dB SNR.The LTC2328-18 has an onboard single-shot capable reference buffer and low drift (20ppm/?C max) 2.048V temperature compensated reference. The LTC2328-18 also has a high speed SPI-compatible serial interface that supports 1.8V, 2.5V, 3.3V and 5V logic while also featuring a daisy-chain mode. The fast 1Msps throughput with no cycle latency makes the LTC2328-18 ideally suited for a wide variety of high speed applications. An internal oscillator sets the conversion time, easing external timing considerations. The LTC2328-18 dissipates only 50mW and automatically naps between conversions, leading to reduced power dissipation that scales with the sampling rate. A sleep mode is also provided to reduce the power consumption of the LTC2328-18 to 300?W for further power savings during inactive periods. Bits LTC2328-16 16 LTC2328-18 18 Applications Programmable Logic Controllers Industrial Process Control High Speed Data Acquisition Portable or Compact Instrumentation ATE