TThe SSM3582A is a fully integrated, high efficiency, digital input stereo Class-D audio amplifier. The device can operate from a single supply and requires only a few external components, significantly reducing the circuit bill of materials.A proprietary, spread spectrum ?-? modulation scheme enables direct connection to the speaker and ensures state-of-the-art analog performance while lowering radiated emissions compared to other Class-D architectures. An optional ultralow electromagnetic interference (EMI) mode significantly reduces radiated emissions above 100 MHz, enabling longer speaker cable lengths. Audio is transmitted digitally to the amplifier, minimizing the possibility of signal corruption in digital environments. The amplifier provides outstanding analog performance, with a 106 dB signal-to-noise ratio and a low 0.004% total harmonic distortion + noise (THD + N).The SSM3582A operates from a single 4.5 V to 16.5 V supply and is capable of delivering 2? 15 W rms continuously into 8 ? and 4 ? loads at The pulse code modulation (PCM) audio serial port supports most common protocols, such as I2S, left justified, and time division multiplexing (TDM), and can address up to 16 devices on a single interface, for up to 32 audio playback channels.IC operation is controlled through a dedicated I2C interface. The two ADDRx pins (2?, five-level) define up to 16 individual addresses in I2C and standalone modes and automatically set the default TDM slots attribution.A micropower shutdown mode is triggered by removing the digital audio interface clock, with a typical current of An automatic power-down feature shuts down the amplifier and the digital-to-analog converter (DAC) when no signal is present at the input, minimizing power consumption during digital silence. The device restarts when nonzero data is present at the input. Mute and unmute transitions are pop and click free.The SSM3582A is specified over the commercial temperature range of ?40?C to +85?C. The device has built in thermal shutdown and output short-circuit protection, as well as an early thermal warning with programmable gain limiting to maintain operation.The SSM3582A is available in a 40-lead, 6 mm ? 6 mm lead frame chip scale package (LFCSP), with a thermal pad to improve heat dissipation.Applications Mobile computing All in one computers Portable electronics Wireless speakers Televisions

HIP2104 Evaluation Board for 12LD TDFN Package

Demonstration circuit 1812A-C features the LTC2943-1. The LTC2943-1 has an operating range of 3.6V to 20V making it perfectly suited for multicell battery applications. A precision analog coulomb counter integrates current measured through the internal sense resistor. The LTC2943-1 measures voltage, current and temperature with an internal 14-bit No Latency ΔΣ™ ADC. The measurements are stored in internal registers accessible via the onboard SMBus/I2C interface.

Demonstration Circuit 2164A-A features a PolyPhase® design using two paralleled LTM4630EY-1's (A-grade), the high efficiency, high density, dual 18A, switch mode step-down power module regulator. The input voltage is from 4.5V to 15V. The output voltage is jumper selectable and can be set to 0.9V, 1.0V, 1.2V, 1.5V or 1.8V. DC2164A-A can deliver nominal 70A output current. As explained in the data sheet, output current derating is necessary for certain VIN, VOUT, and thermal conditions. The LTM4630-1A on DC2164A-A always operate in continuous conduction mode. The switching frequency can be programmed through a resistor or can be synchronized to an external clock signal. The board allows the user to program how its output voltage ramps up and down through the TRACK pin.

Target Development Board (MSP-TS430RGE24A) and MSP-FET Bundle (Microcontrollers Not Included)​

The HMC539ALP3/539ALP3E is a broadband5-bit GaAs IC digital attenuator in a low cost leadless surface mount package. This single positive control line per bit digital attenuator utilizes an offchip AC ground capacitor for near DC operation,making it suitable for a wide variety of RF and IFapplications. Covering DC to 4 GHz, the insertion loss is less than 0.7 dB typical. The attenuatorbit values are 0.25 (LSB), 0.5, 1, 2, and 4 dB for atotal attenuation of 7.75 dB. Attenuation accuracy isexcellent at ? 0.05 dB typical step error. The attenu-ator also features a high IIP3 of +62 dBm. Five TTL/CMOS control inputs are used to select each attenuation state. A single Vdd bias of +3V to +5V is required.Applications Cellular infrastructure ISM, MMDS, WLAN, WiMAX, WiBro Microwave radio and VSAT Test equipment and sensors

The ADAR4002 is a very low power broadband bi-directional single channel true time delay unit (TDU) and a digital step attenuator (DSA). The IC has 18.5 GHz of bandwidth over a frequency range of 0.5 GHz to 19 GHz with 50 ? input impedance at both RF ports. The TDU has two programmable maximum time delays, each with 7-bit control: Range 0 has a maximum delay of 508ps with a resolution of 4ps. This range is used at lower frequencies and where the ADAR4002 has less loss. Range 1 has a maximum delay of 254ps and a resolution of 2ps. This range has less loss compared to Range 0 and is useful at higher frequencies. The DSA has 6-bit resolution with an attenuation range of 0 dB to 31.5 dB and a step size of 0.5 dB. The ADAR4002 is designed to provide flexible digital control through either a SPI interface or a shift register to allow daisy chaining multiple chips together. The ADAR4002 contains register memory for 32 TDU+DSA states. The memory combined with on-chip sequencers, allows a fast memory advance via the UPDATE pin.The ADAR4002 is available in a 2 mm ? 3 mm 14-lead LFCSP package and is specified from -40?C to 85?C.APPLICATIONSElectronic steerable antenna arraysMulti-Function ArraysSATCOMRADARData LinksTest Equipment

The ADF7030-1 is a fully integrated, radio transceiver achieving high performance at very low power. The ADF7030-1 is ideally suited for applications that require long range, network robustness, and long battery life. It is suitable for applications that operate in the ISM, SRD, and licensed frequency bands at 169.4 MHz to 169.6 MHz, 426 MHz to 470 MHz, and 863 MHz to 960 MHz. It provides extensive support for standards-based protocols like IEEE802.15.4g while also providing flexibility to support a wide range of proprietary protocols.The highly configurable low intermediate frequency (IF) receiver supports a large range of receiver channel bandwidths from 2.6 kHz to 406 kHz. This range of receiver channel bandwidths allows the ADF7030-1 to support ultranarrow-band, narrow-band, and wideband channel spacing.The ADF7030-1 features two independent PAs supporting output power ranges of ?20 dBm to +13 dBm and ?20 dBm to +17 dBm. The PAs support ultrafine adjustment of the power with a step resolution of 0.1 dB. The PA output power is exceptionally robust over temperature and voltage. The PAs have an automatic power ramp control to limit spectral splatter to meet regulatory standards.The ADF7030-1 features an on-chip ARM??Cortex?-M0 processor that performs radio control, radio calibration, and packet management. Cortex-M0 eases the processing burden of the host processor because the ADF7030-1 integrates the lower layers of a typical communication protocol stack. This internal processor also permits the download and execution of Analog Devices, Inc., provided firmware modules that can extend the functionality of the ADF7030-1.The ADF7030-1 has two packet modes: generic packet mode and IEEE802.15.4g mode. In generic packet mode, the packet format is highly flexible and fully programmable, thereby ensuring its compatibility with proprietary packet formats. In IEEE802.15.4g packet mode, the packet format conforms to the?IEEE802.15.4g standard. FEC, as per the IEEE802.15.4g standard, is also supported.The ADF7030-1 operates with a power supply range of 2.2 V to 3.6 V and has very low power consumption in both Tx and Rx modes, enabling long lifetimes in battery-operated systems. An ultralow power deep sleep mode achieves a typical current of 10 nA with the configuration memory retained.A complete wireless solution can be built using a small number of external discrete components and a host processor (typically a microcontroller). The host processor can configure the ADF7030-1 using a simple command-based protocol over a standard 4-wire SPI interface. A single-byte command transitions the radio between states or performs a radio function.The ADF7030-1 is available in two package types: a 6 mm ? 6 mm, 40-lead LFCSP and a 7 mm ? 7 mm, 48-lead LQFP. Both package types use NiPdAu plating to mitigate against silver migration in high humidity applications. The ADF7030-1 operating temperature range is ?40?C to +85?C.For Figure 13 to Figure 19, Figure 30, Figure 42, Figure 60, Figure 61, and Figure 75 in the Typical Performance Characteristics section, PA_COARSE is a programmable value that provides a coarse adjustment of the PA output power. This value can be programmed in the range of 1 to 6 for PA1, and from 1 to 10 for PA2. PA_FINE is a programmable value that provides a fine adjustment of the PA output power. This value can be programmed in the range of 3 to 127 for both PA1 and PA2. PA_MICRO is a programmable value that provides a microadjustment (typically <0.1 dB) of the PA output power. This value can be programmed in the range of 1 to 31 for both PA1 and PA2. PAOLDO_VOUT_CON is a programmable value that configures the internal LDO voltage that provides bias for the PA. For additional information on these bit settings, see the ADF7030-1 Software Reference Manual, which is the detailed programming guide for the device.Applications IEEE 802.15.4g (MR-FSK PHY)? Wireless M-Bus (EN 13757-4) Smart metering Security and building automation? Active tag asset tracking Industrial control Wireless sensor networks (WSNs)

TPS7A7002 Low-Dropout (LDO) Linear Regulator Evaluation Module

Ethernet Development Tools Eval-2-Port Ethernet Controller