Analog Devices Inc.

Dual DPLL Digitized Clock Synchronizer Features:Digitized clock transport subsystem9 independent UTS blocks (time stamp egress ports)2 independent IUTS blocks (time stamp ingress ports)Dual DPLL synchronizes 1 Hz to 750 MHz physical layer clocks, providing frequency translation with jitter cleaning of noisy referencesComplies with ITU-T G.8262 and Telcordia GR-253Supports Telcordia GR-1244, ITU-T G.812, ITU-T G.813, ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppb (5 × 108)Both DPLLs feature a 24-bit fractional divider with 24-bit programmable modulusProgrammable digital loop filter bandwidth: 0.0001 Hz to 1850 Hz2 independent, programmable auxiliary NCOs (1 Hz to 65,535 Hz, resolution Automatic and manual holdover and reference switchover, providing zero delay, hitless, or phase buildout operationProgrammable priority-based reference switching with manual, automatic revertive, and automatic nonrevertivemodes supported5 pairs of clock output pins with each pair useable as differential LVDS/HCSL/CML or as 2 single-ended outputs (1 Hz to 500 MHz)2 differential or 8 single-ended input referencesCrosspoint mux interconnects reference inputs to PLLsSupports embedded (modulated) input/output clock signalsFast DPLL locking modesProvides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with thefrequency stability and accuracy of a TCXO or OCXOExternal EEPROM support for autonomous initializationSingle 1.8 V power supply operation with internal regulationBuilt in temperature monitor and alarm and temperature compensation for enhanced zero delay performance

* $42.05 - * $40.02