PTLV9052IDR
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Technical Specifications
| Lead Free Status | No |
| ROHS Compliance | No |
| Approx. price(US$) | 0.17 | 1ku |
| Architecture | CMOS |
| Features | Cost Optimized,EMI Hardened |
| GBW(Typ)(MHz) | 5 |
| Input bias current(Max)(pA) | 0.5 |
| Input common mode headroom (to negative supply)(Typ)(V) | -0.1 |
| Input common mode headroom (to positive supply)(Typ)(V) | 0.1 |
| Iq per channel(Max)(mA) | 0.450 |
| Iq per channel(Typ)(mA) | 0.330 |
| Number of channels(#) | 2 |
| Offset drift(Typ)(uV/C) | 1 |
| Operating temperature range(C) | -40 to 125 |
| Output current(Typ)(mA) | 50 |
| Output swing headroom (to negative supply)(Typ)(V) | 0.03 |
| Output swing headroom (to positive supply)(Typ)(V) | -0.03 |
| Package Group | SOIC|8,TSSOP|8,VSSOP|8,WSON|8 |
| Package size | mm2 |
| Rail-to-rail | In,Out |
| Rating | Catalog |
| Slew Rate(Typ)(V/us) | 13 |
| Total Supply Voltage(Max)(+5V=5, +/-5V=10) | 5.5 |
| Total Supply Voltage(Min)(+5V=5, +/-5V=10) | 1.8 |
| Vn at 1 kHz(Typ)(nV/rtHz) | 20 |
| Vos (offset voltage @ 25 C)(Max)(mV) | 1.5 |


