The HMC374(E) is a general purpose broad band Low Noise Amplifier (LNA) for use in the 0.3 - 3.0 GHz frequency range. The LNA provides 15 dB of gain and a 1.5 dB noise figure from a single positive supply of +2.75 to +5.5V. The low noise figure coupled with a high P1dB (22 dBm) and high OIP3 (37 dBm) make this part ideal for cellular applications. The compact LNA design utilizes on-chip matching for repeatable gain and noise figure performance. To minimize board area the design is offered in a low cost SOT26 package that occupies only 0.118? x 0.118?.Applications Cellular/PCS/3G? WCS, MMDS & ISM? Fixed Wireless & WLAN? Private Land Mobile Radio

TPS51200 Sink Source DDR Termination Regulator

AMC1204 evaluation module for 1-bit; 20-MHz; second-order; isolated delta-sigma modulator

MP34DT01-M Microphone Audio Platform Evaluation Expansion Board

RAA211650 - 1 Non-Isolated Output DC/DC, Step Down Evaluation Board

TPS2544 USB Charging Port Controller & Power Switch Evaluation Module

The LTM4650-1A/LTM4650-1B is dual 25A or single 50A output step-down ?Module? (power module) regulator with ?0.8% (LTM4650-1A) and ?1.5% (LTM4650-1B) total DC output error with ?3% transient output error. Included in the package are the switching controller, power FETs, inductors, and all supporting components. External compensation allows for fast transient response to minimize output capacitance when powering FPGAs, ASICs, and processors. With synchronized multiphase parallel current sharing, six LTM4650-1 devices can deliver up to 300A. The LTM4650-1 is offered in a 16mm ? 16mm ? 5.01 BGA package, with SnPb (BGA) or RoHS compliant terminal finish. VIN Range VOUT Range Comp DC VOUT Accy LTM4650 4.5V to 15V 0.6V to 1.8V Internal 1.5% LTM4650-1B 4.5V to 15V 0.6V to 1.8V External 1.5% LTM4650-1A 4.5V to 15V 0.6V to 1.8V External 0.8% LTM4650A 4.5V to 16V 0.6V to 5.5V Internal 1% LTM4650A-1 4.5V to 16V 0.6V to 5.5V External 1% Applications FPGA, ASIC, ?Processor Core Voltage Regulation Information, Communication Systems

Evaluation Board for the LP38502

The AD9520-11 provides a multioutput clock distributionfunction with subpicosecond jitter performance, along with anon-chip PLL and VCO. The on-chip VCO tunes from 2.27 GHzto 2.65 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHzcan also be used.The AD9520 serial interface supports both SPI and I2C? ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset.The AD9520 features 12 LVPECL outputs in four groups. Anyof the 1.6 GHz LVPECL outputs can be reconfigured as two250 MHz CMOS outputsEach group of outputs has a divider that allows both the divideratio (from 1 to 32) and the phase (coarse delay) to be set.The AD9520 is available in a 64-lead LFCSP and can be operatedfrom a single 3.3 V supply. The external VCO can have anoperating voltage up to 5.5 V. A separate output driver powersupply can be from 2.375 V to 3.465 VThe AD9520 is specified for operation over the standard industrialrange of ?40?C to +85?C.1The AD9520 is used throughout this data sheet to refer to all the members of the AD9520 family. However, when AD9520-1 is used, it is referring to that specificmember of the AD9520 family.ApplicationsLow jitter, low phase noise clock distributionClock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocolsForward error correction (G.710)Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEsHigh performance wireless transceiversATE and high performance instrumentationBroadband infrastructures

The ADIN1300 is a low power, single port, Gigabit Ethernet transceiver with low latency and power consumption specifications primarily designed for industrial Ethernet applications.This design integrates an energy efficient Ethernet (EEE) physical layer device (PHY) core with all associated common analog circuitry, input and output clock buffering, management interface and subsystem registers, and MAC interface and control logic to manage the reset and clock control and pin configuration.The ADIN1300 is available in a 6 mm ? 6 mm, 40-lead lead frame chip scale package (LFCSP). The device operates with a minimum of 2 power supplies, 0.9 V and 3.3 V, assuming the use of a 3.3 V MAC interface supply. For maximum flexibility in system level design, a separate VDDIO supply enables the management data input/output (MDIO) and MAC interface supply voltages to be configured independently of the other circuitry on the ADIN1300, allowing operation at 1.8 V, 2.5 V, or 3.3 V. At power-up, the ADIN1300 is held in hardware reset until each of the supplies has crossed its minimum rising threshold value. Brown-out protection is provided by monitoring the supplies to detect if one or more supply drops below a minimum falling threshold (see Table 17 on the datasheet), and holding the device in hardware reset until the power supplies return and satisfy the power-on reset (POR) circuit.The MII management interface (also referred to as MDIO interface) provides a 2-wire serial interface between a host processor or MAC (also known as management station (STA)) and the ADIN1300, allowing access to control and status information in the PHY core management registers. The interface is compatible with both the IEEE 802.3 Standard Clause 22 and Clause 45 management frame structures.The ADIN1300 can support cable lengths up to 150 meters at Gigabit speeds and 180 meters when operating at 100 Mbps or 10 Mbps.Applications Industrial automation Process control Factory automation Robotics/Motion Control Building automation Test and Measurement Industrial IoT