The ADN2812 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 automatically locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for ?40?C to +85?C ambient temperature, unless otherwise noted. This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power fiber optic receiver. The receiver front end, loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a user-adjustable threshold. The LOS detect circuit has hysteresis to prevent chatter at the output. The ADN2812 is available in a compact 5 mm ? 5 mm 32-lead lead frame chip scale package (LFCSP).ApplicationsSONET OC-1/OC-3/OC-12/OC-48 and all associated FEC rates Fibre Channel, 2? Fibre Channel, GbE, HDTV WDM transponders Regenerators/repeaters Test equipment Broadband cross-connects and routers

F28069 Piccolo controlSTICK

AMC7834 12-Bit Integrated Power-Amplifier Analog Monitor and Control (AMC) System Evaluation Module

Dual Brushed DC Motor BoosterPack featuring DRV8848

The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 3G, 4G, and 5G macro cell time division duplex (TDD) base station applications.The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The device also supports a wide bandwidth, time shared observation path receiver (ORx) for use in TDD applications. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, thus eliminating the need?for these functions in the digital baseband. Several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for the power amplifier (PA), and RF front-end control are also integrated.In addition to automatic gain control (AGC), the ADRV9009 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.The received signals are digitized with a set of four high dynamic range, continuous time ?-? ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing, relaxes the requirements of the RF filters when compared to traditional intermediate frequency (IF) receivers.The transmitters use an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise.The observation receiver path consists of a wide bandwidth, direct conversion receiver with state-of-the-art dynamic range.The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N RF frequency synthesis for the transmitter (Tx) and receiver (Rx) signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9009 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, thus reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.The core of the ADRV9009 can be powered directly from 1.3 V regulators and 1.8 V regulators, and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9009 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G, 4G, and 5G TDD macrocell base stations TDD active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

DS90UB928QEVM FPD-Link III Deserializer Evaluation Module

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Power Management IC Development Tools FRDMGD31RPEVM

The AD5423 is a single-channel, voltage and current output digital-to-analog converter (DAC) that operates with a power supply range from ?33 V minimum on AVSS to +33 V maximum on AVDD1. The CHART pin enables a Highway Addressable Remote Transducer? (HART) signal to be coupled on the current output. The AD5423 uses a versatile, 4-wire, serial peripheral interface (SPI) that operates at clock rates of up to 50 MHz and is compatible with standard SPI, QSPI?, MICROWIRE?, digital signal processor (DSP), and microcontroller interface standards. The interface also features an optional SPI cyclic redundancy check (CRC) and a watchdog timer (WDT). The AD5423 offers improved diagnostic features from earlier versions of similar DACs, such as an integrated, 12-bit diagnostic analog-to-digital converter (ADC).Product Highlights 16-bit performance. Range of diagnostic features. Integrated 12-bit monitoring ADC. HART compliant.Applications Process control Actuator control Channel isolated analog outputs Programmable logic controller (PLC) and distributed control systems (DCS) applications HART network connectivity

The HMC682LP6C(E) is a high linearity, dual channel downconverter with integrated LO amplifier in a 6?6 SMT QFN package covering 1.7 - 2.2 GHz. Excellent input IP3 performance of +25 dBm for down conversion is provided for 3G & 4G GSM/CDMA applications at an LO drive of 0 dBm. With an input 1 dB compression of +15 dBm, the RF port will accept a wide range of input signal levels. Conversion gain is 6 dB typical. The 60 - 400 MHz IF frequency response will satisfy various GSM/CDMA receive frequency plans.APPLICATIONS Cellular/3G & LTE/WiMAX/4G Basestations & Repeaters GSM, CDMA & OFDM Dual Density Receivers