TRF1216 Evaluation Module

The AD9737A/AD9739A are 11-bit and 14-bit, 2.5 GSPS high performance RF DACs that are capable of synthesizing wideband signals from dc up to 3 GHz. The AD9737A/AD9739A are pin and functionally compatible with the AD9739 with the exception that the AD9737A/AD9739A do not support synchronization or RZ mode, and are specified to operate between 1.6 GSPS and 2.5 GSPS. By elimination of the synchronization circuitry, some nonideal artifacts such as images and discrete clock spurs remain stationary on the AD9737A/AD9739A between power-up cycles, thus allowing for possible system calibration. AC linearity and noise performance remain the same between the AD9739 and the AD9737A/AD9739A.The inclusion of on-chip controllers simplifies system integration. A dual-port, source synchronous, LVDS interface simplifies the digital interface with existing FGPA/ASIC technology. On-chip controllers are used to manage external and internal clock domain variations over temperature to ensure reliable data transfer from the host to the DAC core. A serial peripheral interface (SPI) is used for device configuration as well as readback of status registers.The AD9737A/AD9739A are manufactured on a 0.18 ?m CMOS process and operate from 1.8 V and 3.3 V supplies. They are supplied in a 160-ball chip scale ball grid array for reduced package parasitics.Product Highlights Ability to synthesize high quality wideband signals with bandwidths of up to 1.25 GHz in the first or second Nyquist zone. A proprietary quad-switch DAC architecture provides exceptional ac linearity performance while enabling mixmode operation. A dual-port, double data rate, LVDS interface supports the maximum conversion rate of 2500 MSPS. On-chip controllers manage external and internal clock domain skews. Programmable differential current output with an 8.66 mA to 31.66 mA range.Applications Broadband communications systems DOCSIS CMTS systems Military jammers Instrumentation, automatic test equipment Radar, avionics

Demonstration circuit 2365A highlights the LTC2358 family of buffered input ADCs. The LTC2358/LTC2357/LTC2353/LTC2333 are low noise, high speed, 16-/18- bit successive approximation register (SAR) ADCs with integrated front end buffers. These ADCs accept a wide common mode range. Pico-amp inputs and high CMRR enable these ADCs to connect directly to a wide range of sensors without compromising measurement accuracy. The following text refers to the LTC2358-18 but applies to all parts in the family, the only differences being the number of bits, number of channels and the maximum sample rate. The LTC2358-18 has a flexible SoftSpan™ interface that allows conversion-by-conversion control of the input voltage span on a per-channel basis. An internal 2.048V reference and 2X buffer simplify basic operation while an external reference can be used to increase the input range and the SNR of the ADC.

The AD5413 is a single-channel, 14-bit voltage and current output, digital-to-analog converter (DAC) that operates within a power supply range from a ?33 V minimum on the AVSS pin to a +33 V maximum on the AVDD1 pin. The CHART pin enables a highway addressable remote transducer (HART?) signal to be ac-coupled on the current output.The AD5413 uses a versatile, 4-wire serial peripheral interface (SPI) that operates at clock rates of up to 50 MHz and is compatible with standard SPI, QSPI?, MICROWIRE?, digital signal processor (DSP), and microcontroller interface standards. The SPI interface has an optional SPI cyclic redundancy check (CRC). The AD5413 implements improved diagnostic features from earlier versions of similar DACs.APPLICATIONS Process control Actuator control Channel isolated analog outputs Programmable logic controller (PLC) and distributed control systems (DCS) applications HART network connectivity

ADS122C04 evaluation module

Demonstration circuit 862 is a micropower regulated charge pump DC/DC converter featuring the 60mA output LTC3221 in a 2mmx2mm DFN package. It comes in three assembly versions, DC862A-A, DC862A-B and DC862A-C, featuring the LTC3221EDC-3.3 (fixed 3.3V output), the LTC3221EDC-5 (fixed 5V output) , and LTC3221EDC (adjustable output set to 3V), respectively. The demo board input voltage range depends on the IC used; for the 3.3V output DC862A-A, the input voltage range is 1.8V to 4.4V. The LTC3221's low 8µA no-load quiescent current is even lower than the self-discharging current of many batteries. By employing a constant current to charge the output, the output ripple is low even at high input and light load, and is fairly constant over the full input voltage range.

EVAL KIT FOR TLV320AIC33

C5535/C5545 eZdsp USB Stick Development Kit

Sockets & Adapters LIS2DU12 adapter board for a standard DIL 24 socket

The ADN2850 is a dual-channel, nonvolatile memory, digitallycontrolled resistors?with 1024-step resolution, offeringguaranteed maximum low resistor tolerance error of ?8%. Thedevice performs the same electronic adjustment function as amechanical rheostat with enhanced resolution, solid statereliability, and superior low temperature coefficientperformance. The versatile programming of the ADN2850 viaan SPI?-compatible serial interface allows 16 modes ofoperation and adjustment including scratchpad programming,memory storing and restoring, increment/decrement, ?6 dB/steplog taper adjustment, wiper setting readback, and extra EEMEM?for user-defined information such as memory data for other components, look-up table, or system identificationinformation.In the scratchpad programming mode, a specific setting canbe programmed directly to the RDAC?register, which sets theresistance between Terminal W and Terminal B. This setting canbe stored into the EEMEM and is restored automatically to theRDAC register during system power-on.The EEMEM content can be restored dynamically or throughexternal PR strobing, and a WP function protects EEMEM contents. To simplify the programming, the independent orsimultaneous linear-step increment or decrement commandscan be used to move the RDAC wiper up or down, one step at atime. For logarithmic ?6 dB changes in the wiper setting, theleft or right bit shift command can be used to double or halve theRDAC wiper setting.The ADN2850 patterned resistance tolerance is stored in theEEMEM. The actual full scale resistance can, therefore, beknown by the host processor in readback mode. The host canexecute the appropriate resistance step through a softwareroutine that simplifies open-loop applications as well asprecision calibration and tolerance matching applications.The ADN2850 is available in the 5 mm ? 5 mm 16-lead framechip scale LFCSP and thin, 16-lead TSSOP package. The part isguaranteed to operate over the extended industrial temperaturerange of ?40?C to +85?C.Applications SONET, SDH, ATM, Gigabit Ethernet, DWDM laser diode driver, optical supervisory systems Mechanical rheostat replacement Instrumentation gain adjustment Programmable filters, delays, time constants Sensor calibration