The ADAQ23878 is a precision, high speed, ?Module? data acquisition solution that reduces the development cycle of a precision measurement systems by transferring the design burden of component selection, optimization, and layout from the designer to the device.Using System-in-Package (SIP) technology, the ADAQ23878 reduces end system component count by combining multiple common signal processing and conditioning blocks in a single device, including a low noise, fully differential ADC driver (FDA), a stable reference buffer, and a high speed, 18-bit, 15 MSPS successive approximation register (SAR) ADC.The ADAQ23878 also incorporates the critical passive components with superior matching and drift characteristics using Analog Devices, Inc., iPassive? technology to minimize temperature dependent error sources and to offer optimized performance. The fast settling of the ADC driver stage and no latency of the SAR ADC provide a unique solution for high channel count multiplexed signal chain architectures and control loop applications.The small footprint, 9 mm ? 9 mm BGA package enables smaller form factor instruments without sacrificing performance. The system integration solves many design challenges while the device still provides the flexibility of a configurable ADC driver feedback loop to allow gain or attenuation adjustments, as well as fully differential or single-ended to differential input. A single 5 V supply operation is possible while achieving optimum performance from the device.The ADAQ23878 features a serial low voltage differential signaling (LVDS) digital interface with one-lane or two-lane output modes, allowing the user to optimize the interface data rate for each application. The specified operation of the ADAQ23878 is from ?40?C to +85?C.APPLICATIONS Automatic test equipment Data acquisition Hardware in the Loop (HiL) Power analyzers Non-destructive test (acoustic emissions) Mass spectrometry Travelling wave fault location Medical imaging and instruments

The ADAR7251 is a 16-bit, 4-channel, simultaneous sampling analog-to-digital converter (ADC) designed especially for applications such as automotive LSR-FMCW or FSK-FMCW radar systems. Each of the four channels contains a low noise amplifier (LNA), a programmable gain amplifier (PGA), an equalizer, a multibit ?-? ADC, and a decimation filter.The front-end circuitry is designed to allow direct connection to an MMIC output with few external passive components. The ADAR7251 eliminates the need for a high order antialiasing filter, driver op amps, and external bipolar supplies. The ADAR7251 also offers precise channel-to-channel drift matching.The ADAR7251 features an on-chip phase-locked loop (PLL) that allows a range of clock frequencies for flexibility in the system. The CONV_START input and DATA_READY output signals synchronize the ADC with an external ramp for applications such as FSK-FMCW radar.The ADAR7251 supports serial and parallel interfaces at programmable sample rates from 300 kSPS to 1.8 MSPS, as well as easy connections to digital signal processors (DSPs) and microcontroller units (MCUs) in the system.APPLICATIONS Automotive LSR systems Data acquisition systems

The ADATE209 is a dual pin driver designed for testing DDR2, DDR3, and DDR4. It can also be used for high speed SoC applications, such as testing PCI Express 1.0 and HDMI?. The device is a three-level driver capable of high fidelity swings from 200 mV to 4 V over a ?1 V to +3.5 V range. It has rise/fall times (20% to 80%) under 120 ps for a 2 V programmed swing and 150 ps for a 3 V programmed swing, and is capable of supporting data rates of 4.4 Gbps and 3.2 Gbps, respectively.The device is capable of high speed transitions into and out of termination mode. It also contains peaking/pre-emphasis circuitry.The ADATE209 is available in an 8 mm ? 8 mm, 49-ball CSP_BGA.APPLICATIONS Automatic test equipment Semiconductor test systems Board test systems Instrumentation and characterization equipment High speed memory testing (DDR2/DDR3/DDR4) HDMI testing

The ADAU1472 is a high quality SigmaDSP? digital audio?processor with a large internal memory, enabling efficient audio?source separation, far field voice capture, speech processing, deep?learning, and advanced audio signal processing. The processor combines the highly optimized Cadence? Tensilica? HiFi? 4?audio/voice processor with custom Analog Devices, Inc.,?instruction extensions for math acceleration, and a flexible input and output architecture. The?HiFi 4 processor supports four 32-bit ? 32-bit multiplier?accumulators (MACs) per cycle with 72-bit accumulators, dual 64-bit memory load, and a native Institute of Electrical and?Electronics Engineers (IEEE) single precision, floating-point multiplier.The ADAU1472 processor offers performance up to 270.336 MHz,?supports low latency, sample by sample audio processing, and?block by block processing paradigms in parallel. The integer?phase-locked loop (PLL) and flexible clock generator hardware?can generate up to 15 audio sample rates simultaneously (8 kHz?to 192 kHz). These clock generators, along with the on-board?asynchronous sample rate converters (ASRCs) and flexible?hardware audio routing matrix, greatly simplify the design of?complex audio systems.The HiFi 4 digital signal processor (DSP) core has 480 kB of L1?memory running at the DSP core clock rate, which consists of?256 kB data random access memory (RAM), 64 kB instruction?RAM, 128 kB data cache, and 32 kB instruction cache, along with?2 MB of L2 system static random access memory (SRAM)?running at one half of the DSP core clock rate. The processor?also supports up to 2 GB of external flash memory to enable the?storage of large data tables and self boot code.Dual on-chip power domains allow low power operation,?including the capability of routing audio through a flexible audio?routing matrix with IOVDD as the only active supply.?The configurable voice detection hardware can detect human?speech onset while operating in a low power state and can?generate both internal DSP and external wake-up signals.The ADAU1472 interfaces with a wide range of analog-to-digital?converters (ADCs), digital-to-analog converters (DACs), digital?audio devices, amplifiers, and control circuitry due to its highly?configurable serial ports, Sony/Philips digital interface?format (S/PDIF) interfaces, and multipurpose input/output?pins. The device can also directly interface with up to 14 pulse?density modulated (PDM) output microphones due to?integrated decimation filters specifically designed for that?purpose. The PDM outputs with integrated interpolation filters?provide direct connectivity to PDM input Class D amplifiers.The processor has two serial peripheral interface (SPI) bus master?control ports that allow the device to communicate with multiple?SPI-compatible devices including support for single, dual, and?quad input/output operation. In addition, the SPI flash port?allows direct memory mapped read access with minimal central?processing unit (CPU) overhead and standalone self boot?operation.The combined high performance DSP core, large RAM, and?small footprint make the ADAU1472 an ideal replacement for?large, general-purpose DSPs that consume more power for the?same processing load.Applications Far field voice interface devices Audio source separation Embedded deep learning for audio Commercial and professional audio processing

The ADAU7112 converts stereo pulse density modulation (PDM) bitstreams into one pulse code modulation (PCM) output stream. The source for the PDM data can be two microphones or other PDM sources. The PCM audio data is output on a serial audio interface port in either inter-IC serial (I2S) or time domain multiplexed (TDM) format. The ADAU7112 is specified over the commercial temperature range (?40?C to +85?C). The ADAU7112 is available in a halide-free, 9-ball, 1.26 mm ? 1.26 mm, 0.4 mm pitch, wafer level chip scale package (WLCSP).Applications? Mobile computing Portable electronics Consumer electronics Professional electronics

The ADCMP551?/ ADCMP552 / ADCMP553?are single supply,high speed comparators fabricated on Analog Devices?proprietary XFCB process. The devices feature a 750 ps propagation delay with less than 150 ps overdrive dispersion. Dispersion, a measure of the difference in propagation delay under differing overdrive conditions, is a particularly importantcharacteristic of high speed comparators. A separateprogrammable hysteresis pin is available on the ADCMP552.A differential input stage permits consistent propagation delay with a common-mode range from ?0.2 V to VCCI ? 2.0 V. Outputs are complementary digital signals are fully compatiblewith PECL 10 K and 10 KH logic families. The outputs provide sufficient drive current to directly drive transmission lines terminated in 50 . to VCCO - 2 V. A latch input is includedand permits tracking, track-and-hold, or sample-and-hold modes of operation. The latch input pins contain internal pullups that set the latch in tracking mode when left open.The ADCMP551 / ADCMP552 / ADCMP553 are specified overthe ?40?C to +85?C industrial temperature range. TheADCMP551 is available in a 16-lead QSOP package; theADCMP552 is available in a 20-lead QSOP package; and the ADCMP553 is available in an 8-lead MSOP package.APPLICATIONS Automatic test equipment High speed instrumentation Scope and logic analyzer front ends Window comparators High speed line receivers Threshold detection Peak detection High speed triggers Patient diagnostics Disk drive read channel detection Hand-held test instruments Zero crossing detectors Line receivers and signal restoration Clock drivers?

The ADF7012 is a low power FSK/GFSK/OOK/GOOK/ASK UHF transmitter designed for short-range devices (SRDs). The output power, output channels, deviation frequency, and modulation type are programmable by using four, 32-bit registers.The fractional-N PLL and VCO with external inductor enable the user to select any frequency in the 75 MHz to 1 GHz band. The fast lock times of the fractional-N PLL make the ADF7012 suitable in fast frequency hopping systems. The fine frequency deviations available and PLL phase noise performance facilitates narrow-band operation.There are five selectable modulation schemes: binary frequency shift keying (FSK), Gaussian frequency shift keying (GFSK), binary on-off keying (OOK), Gaussian on-off keying (GOOK), and amplitude shift keying (ASK). In the compensation register, the output can be moved in <1 ppm steps so that indirect compensation for frequency error in the crystal reference can be made.A simple 3-wire interface controls the registers. In power-down, the part has a typical quiescent current of <0.1 ?A.APPLICATIONS Low cost wireless data transfer Security systems RF remote controls Wireless metering Secure keyless entry

The ADF7020 is a low power, low-IF transceiver designed for operation in the license-free ISM bands at 433MHz, 868MHz and 915MHz. It is suitable for circuit applications that meet either the European ETSI EN-300-220 or the North American FCC, Part 15.247 and 15.249 regulatory standards. It operates from a 2.3 V to 3.6V power supply with programmable output power from -16 to +13dBm in 0.3dBm steps. Its receiver sensitivity is -117.5dBm at 1kbits/s in FSK mode or -110.5dBm at 9.6kbits/s. Power consumption is 20mA in receive mode and 30mA in transmit mode (+10dBm output).Other features include on-chip VCO (voltage controlled oscillator), Fractional-N PLL, on-chip 7-bit ADC (analog-to-digital converter), digital received signal strength indication (RSSI), temperature sensor and a patent pending fully automatic AFC loop. This allows the ADF7020 to be used with lower tolerance crystals. Its leakage current is < 1uA in power down mode.This device is suitable for circuit applications that meet the European ETSI-300-220, the North American FCC (Part 15), or the Chinese Short Range Device regulatory standards. A complete transceiver can be built using a small number of external discrete components, making the ADF7020 very suitable for price-sensitive and area-sensitive applications. The transmitter block on the ADF7020 contains a VCO and low noise fractional-N PLL with an output resolution of <1 ppm. This frequency agile PLL allows the ADF7020 to be used in frequency-hopping spread spectrum (FHSS) systems. The VCO operates at twice the fundamental frequency to reduce spurious emissions and frequency-pulling problems.The transmitter output power is programmable in 0.3 dB steps from ?16 dBm to +13 dBm. The transceiver RF frequency and modulation are programmable using a simple 3-wire interface. The device operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use.A low IF architecture is used in the receiver (200 kHz), minimizing power consumption and the external component count and avoiding interference problems at low frequencies. The ADF7020 supports a wide variety of programmable features, including Rx linearity, sensitivity, and IF bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. The receiver also features a patent-pending automatic frequency control (AFC) loop, allowing the PLL to track out the frequency error in the incoming signal.An on-chip ADC provides readback of an integrated temperature sensor, an external analog input, the battery voltage, or the RSSI signal, which provides savings on an ADC in some applications. The temperature sensor is accurate to ?10?C over the full operating temperature range of ?40?C to +85?C. This accuracy can be improved by doing a 1-point calibration at room temperature and storing the result in memory.APPLICATIONS Low cost wireless data transfer Remote control/security systems Wireless metering Keyless entry Home automation Process and building control Wireless voice

The ADF7021 is a low power, highly integrated 2FSK/3FSK/4FSK transceiver. It is designed to operate in the narrowband, license-free ISM bands and licensed bands in the 80 MHz to 650 MHz and 862 MHz to 940 MHz frequency ranges. It has both Gaussian and raised cosine data filtering options to improve spectral efficiency for narrowband applications.It is suitable for circuit applications targeted at European ETSI-EN 300-220, the Japanese ARIB STD-T67, the Chinese Short Range Device regulations, and the North American FCC Part 15, Part 90, and Part 95 regulatory standards. A complete transceiver can be built using a small number of external discrete components, making the ADF7021 very suitable for price-sensitive and area-sensitive applications.The transmit section contains a voltage controlled oscillator (VCO) and a low noise fractional-N PLL with output resolution of <1 ppm. This frequency-agile PLL allows the ADF7021 to be used in frequency hopping spread spectrum (FHSS) systems. The VCO operates at twice the fundamental frequency to reduce spurious emissions and frequency pulling problems. The transmitter output power is programmable in 63 steps from ?16 dBm to +13 dBm and has an automatic power ramp control to prevent spectral splatter and help meet regulatory standards. The transceiver RF frequency, channel spacing, and modulation are programmable using a simple 3-wire interface. The device operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use.A low IF architecture is used in the receiver (100 kHz), minimizing power consumption and the external component count while avoiding interference problems at low frequencies. The IF filter has programmable bandwidths of 12.5 kHz, 18.75 kHz, and 25 kHz. The ADF7021 supports a wide variety of programmable features including Rx linearity, sensitivity, and IF bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. The receiver also features a patent-pending automatic frequency control (AFC) loop with programmable pull-in range, allowing the PLL to track out the frequency error in the incoming signal.An on-chip ADC provides readback of an integrated temperature sensor, an external analog input, the battery voltage, and the RSSI signal, which provides savings on an ADC in some applications. The temperature sensor is accurate to ?10?C over the full operating temperature range of ?40?C to +85?C. This accuracy can be improved by doing a 1-point calibration at room temperature and storing the result in memory.

The ADF7021-N is a high performance, low power, narrow-band transceiver based on the ADF7021. The ADF7021-N has IF filter bandwidths of 9 kHz, 13.5 kHz, and 18.5 kHz, making it ideally suited to worldwide narrowband standards and particularly those that stipulate 12.5 kHz channel separation. It is designed to operate in the narrow-band, license-free ISM bands and in the licensed bands with frequency ranges of 80 MHz to 650 MHz and 842 MHz to 916 MHz. The part has both Gaussian and raised cosine transmit data filtering options to improve spectral efficiency for narrow-band applications. It is suitable for circuit applications targeted at the Japanese ARIB STD-T67, the European ETSI EN 300 220, the Korean short range device regulations, the Chinese short range device regulations, and the North American FCC Part 15, Part 90, and Part 95 regulatory standards. A complete transceiver can be built using a small number of external discrete components, making the ADF7021-N very suitable for price-sensitive and area-sensitive applications. The range of on-chip FSK modulation and data filtering options allows users greater flexibility in their choice of modulation schemes while meeting the tight spectral efficiency requirements. The ADF7021-N also supports protocols that dynamically switch among 2FSK, 3FSK, and 4FSK to maximize communica-tion range and data throughput. The transmit section contains two voltage controlled oscillators (VCOs) and a low noise fractional-N PLL with an output resolution of The frequency-agile PLL allows the ADF7021-N to be used in frequency-hopping, spread spectrum (FHSS) systems. Both VCOs operate at twice the fundamental frequency to reduce spurious emissions and frequency pulling problems. The transmitter output power is programmable in 63 steps from ?16 dBm to +13 dBm and has an automatic power ramp control to prevent spectral splatter and help meet regulatory standards. The transceiver RF frequency, channel spacing, and modulation are programmable using a simple 3-wire interface. The device operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use. A low IF architecture is used in the receiver (100 kHz), which minimizes power consumption and the external component count yet avoids dc offset and flicker noise at low frequencies. The IF filter has programmable bandwidths of 9 kHz, 13.5 kHz, and 18.5 kHz. The ADF7021-N supports a wide variety of pro-grammable features including Rx linearity, sensitivity, and IF bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. The receiver also features a patent-pending automatic frequency control (AFC) loop with programmable pull-in range that allows the PLL to track out the frequency error in the incoming signal. The receiver achieves an image rejection performance of 56 dB using a patent-pending IR calibration scheme that does not require the use of an external RF source. An on-chip ADC provides readback of the integrated tempera-ture sensor, external analog input, battery voltage, and RSSI signal, which provides savings on an ADC in some applications. The temperature sensor is accurate to ?10?C over the full oper-ating temperature range of ?40?C to +85?C. This accuracy can be improved by performing a 1-point calibration at room temperature and storing the result in memory.