The ADRV9029 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations.The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs.The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/ outputs (GPIOs) that provide an array of digital control options are also integrated.To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface.A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9029 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface.This device contains a fully integrated, low power digital predistortion (DPD) adaptation engine for use in power amplifier linearization. DPD enables use of high efficiency power amplifiers, reducing the power consumption of base station radios while also reducing the number of SERDES lanes necessary to interface with baseband processors.The low power crest factor reduction (CFR) engine of the ADRV9029 reduces the peak to average ratio (PAR) of the input signal, enabling higher efficiency transmit line ups while reducing the processing load on baseband processors.The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device.The ADRV9029 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9029 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).APPLICATIONS3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

The ADV3200/ADV3201 are 32 ? 32 analog crosspoint switch matrices. They feature a selectable sync-tip clamp input forac-coupled applications and an on-screen display (OSD) insertion mux. With ?48 dB of crosstalk and ?80 dB isolationat 5 MHz, the ADV3200/ADV3201 are useful in many high density routing applications. The 0.1 dB flatness out to 60 MHz makes the ADV3200/ADV3201 ideal for composite video switching.The 32 independent output buffers of the ADV3200/ADV3201 can be placed into a high impedance state for paralleling crosspoint outputs so that off-channels present minimal loading to an output bus if building a larger array. The part is available in gain of +1 (ADV3200) or +2 (ADV3201) for ease of use in back-terminated load applications. A single 5 V supply, dual ?2.5 V supplies, or dual ?3.3 V supplies (G = +2) can be used while consuming only 250 mA of idle current with all outputs enabled. The channel switching is performed via a double buffered, serial digital control, which can accommodate daisy chaining of several devices. The ADV3200/ADV3201 are packaged in a 176-lead exposed pad LQFP (24 mm ? 24 mm) and are available over the extended industrial temperature range of ?40?C to +85?C.Applications CCTV surveillance Routing of high speed signals including ????????Composite video (NTSC, PAL, S, SECAM) ????????RGB and component video routing ????????Compressed video (MPEG, Wavelet) Video conferencing?

Demonstration circuit 1021A is a high efficiency synchronous step-down DC/DC converter with 4.5V to 16V input range. It can provide 2.5V output with 10A maximum current. The demo board features the LTC3823EUH controller.

The LT3513 5-output adjustable switching regulator provides power for large TFT-LCD panels. The 38-pin 5mm ? 7mm QFN device can generate a 3.3V or 5V logic supply along with the triple output supply required for the TFT-LCD panel. A lower voltage secondary logic supply may also be generated with the addition of an external NPN driven by the internal linear regulator. A step-down regulator provides a low voltage output, VLOGIC, with up to 1.2A of current while capable of operating from a wide input range of 4.5V to 30V. A high power step-up converter, a lower power step-up converter and an inverting converter provide the three independent output voltages: AVDD, VON and VOFF required by the LCD panel. A high-side PNP provides delayed turn-on of the VON signal and can handle up to 30mA. Protection circuitry ensures that VON is disabled if any of the four outputs are more than 10% below the programmed voltage.Applications Automotive TFT-LCD Displays Large TFT-LCD Desktop Monitors Flat Panel Televisions

The ADF7020 is a low power, low-IF transceiver designed for operation in the license-free ISM bands at 433MHz, 868MHz and 915MHz. It is suitable for circuit applications that meet either the European ETSI EN-300-220 or the North American FCC, Part 15.247 and 15.249 regulatory standards. It operates from a 2.3 V to 3.6V power supply with programmable output power from -16 to +13dBm in 0.3dBm steps. Its receiver sensitivity is -117.5dBm at 1kbits/s in FSK mode or -110.5dBm at 9.6kbits/s. Power consumption is 20mA in receive mode and 30mA in transmit mode (+10dBm output).Other features include on-chip VCO (voltage controlled oscillator), Fractional-N PLL, on-chip 7-bit ADC (analog-to-digital converter), digital received signal strength indication (RSSI), temperature sensor and a patent pending fully automatic AFC loop. This allows the ADF7020 to be used with lower tolerance crystals. Its leakage current is < 1uA in power down mode.This device is suitable for circuit applications that meet the European ETSI-300-220, the North American FCC (Part 15), or the Chinese Short Range Device regulatory standards. A complete transceiver can be built using a small number of external discrete components, making the ADF7020 very suitable for price-sensitive and area-sensitive applications. The transmitter block on the ADF7020 contains a VCO and low noise fractional-N PLL with an output resolution of <1 ppm. This frequency agile PLL allows the ADF7020 to be used in frequency-hopping spread spectrum (FHSS) systems. The VCO operates at twice the fundamental frequency to reduce spurious emissions and frequency-pulling problems.The transmitter output power is programmable in 0.3 dB steps from ?16 dBm to +13 dBm. The transceiver RF frequency and modulation are programmable using a simple 3-wire interface. The device operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use.A low IF architecture is used in the receiver (200 kHz), minimizing power consumption and the external component count and avoiding interference problems at low frequencies. The ADF7020 supports a wide variety of programmable features, including Rx linearity, sensitivity, and IF bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. The receiver also features a patent-pending automatic frequency control (AFC) loop, allowing the PLL to track out the frequency error in the incoming signal.An on-chip ADC provides readback of an integrated temperature sensor, an external analog input, the battery voltage, or the RSSI signal, which provides savings on an ADC in some applications. The temperature sensor is accurate to ?10?C over the full operating temperature range of ?40?C to +85?C. This accuracy can be improved by doing a 1-point calibration at room temperature and storing the result in memory.APPLICATIONS Low cost wireless data transfer Remote control/security systems Wireless metering Keyless entry Home automation Process and building control Wireless voice

The ADF7021 is a low power, highly integrated 2FSK/3FSK/4FSK transceiver. It is designed to operate in the narrowband, license-free ISM bands and licensed bands in the 80 MHz to 650 MHz and 862 MHz to 940 MHz frequency ranges. It has both Gaussian and raised cosine data filtering options to improve spectral efficiency for narrowband applications.It is suitable for circuit applications targeted at European ETSI-EN 300-220, the Japanese ARIB STD-T67, the Chinese Short Range Device regulations, and the North American FCC Part 15, Part 90, and Part 95 regulatory standards. A complete transceiver can be built using a small number of external discrete components, making the ADF7021 very suitable for price-sensitive and area-sensitive applications.The transmit section contains a voltage controlled oscillator (VCO) and a low noise fractional-N PLL with output resolution of <1 ppm. This frequency-agile PLL allows the ADF7021 to be used in frequency hopping spread spectrum (FHSS) systems. The VCO operates at twice the fundamental frequency to reduce spurious emissions and frequency pulling problems. The transmitter output power is programmable in 63 steps from ?16 dBm to +13 dBm and has an automatic power ramp control to prevent spectral splatter and help meet regulatory standards. The transceiver RF frequency, channel spacing, and modulation are programmable using a simple 3-wire interface. The device operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use.A low IF architecture is used in the receiver (100 kHz), minimizing power consumption and the external component count while avoiding interference problems at low frequencies. The IF filter has programmable bandwidths of 12.5 kHz, 18.75 kHz, and 25 kHz. The ADF7021 supports a wide variety of programmable features including Rx linearity, sensitivity, and IF bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. The receiver also features a patent-pending automatic frequency control (AFC) loop with programmable pull-in range, allowing the PLL to track out the frequency error in the incoming signal.An on-chip ADC provides readback of an integrated temperature sensor, an external analog input, the battery voltage, and the RSSI signal, which provides savings on an ADC in some applications. The temperature sensor is accurate to ?10?C over the full operating temperature range of ?40?C to +85?C. This accuracy can be improved by doing a 1-point calibration at room temperature and storing the result in memory.

The ADF7023 is a very low power, high performance, highly integrated 2FSK/GFSK/OOK/MSK/GMSK transceiver designed for operation in the 862 MHz to 928 MHz and 431 MHz to 464 MHz frequency bands, which cover the worldwide license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz. It is suitable for circuit applications that operate under the European ETSI EN300-220, the North American FCC (Part 15), the Chinese short-range wireless regulatory standards, or other similar regional standards. Data rates from 1 kbps to 300 kbps are supported.The transmit RF synthesizer contains a VCO and a low noise fractional-N PLL with an output channel frequency resolution of 400 Hz. The VCO operates at 2? or 4?, the fundamental frequency to reduce spurious emissions. The receive and transmit synthesizer bandwidths are automatically, and independently, configured to achieve optimum phase noise, modulation quality, and settling time. The transmitter output power is programmable from ?20 dBm to +13.5 dBm, with automatic PA ramping to meet transient spurious specifications. The part possesses both single-ended and differential PAs, which allows for Tx antenna diversity.The receiver is exceptionally linear, achieving an IP3 specification of ?12.2 dBm and ?11.5 dBm at maximum gain and minimum gain, respectively, and an IP2 specification of 18.5 dBm and 27 dBm at maximum gain and minimum gain, respectively. The receiver achieves an interference blocking specification of 66 dB at ?2 MHz offset and 74 dB at ?10 MHz offset. Thus, the part is extremely resilient to the presence of interferers in spectrally noisy environments. The receiver features a novel, high speed, automatic frequency control (AFC) loop, allowing the PLL to find and correct any RF frequency errors in the recovered packet.A patent pending, image rejection calibration scheme is available through a program download. The algorithm does not require the use of an external RF source nor does it require any user intervention once initiated. The results of the calibration can be stored in nonvolatile memory for use on subsequent power-ups of the transceiver.See data sheet for additional information.Applications Smart metering IEEE 802.15.4g Wireless MBUS Home automation Process and building control Wireless sensor networks (WSNs) Wireless healthcare

The ADGS5412 contains four independent single-pole/single-throw (SPST) switches. A serial peripheral interface (SPI) controls the switches. The SPI interface has robust error detection features, including cyclic redundancy check (CRC) error detection, invalidread/write address detection, and serial clock (SCLK) counterror detection.It is possible to daisy-chain multiple ADGS5412 devices together,which enables the configuration of multiple devices with aminimal amount of digital lines. The ADGS5412 can also operate in burst mode to decrease the time between SPIcommands. Each switch conducts equally well in both directions when on,and each switch has an input signal range that extends to thesupplies. In the off condition, signal levels up to the supplies are blocked. The on-resistance profile is very flat over the full analog input range, which ensures good linearity and low distortion when switching audio signals. The ADGS5412 exhibits break-before-make switching action, allowing use of the device in multiplexer applications with external wiring.PRODUCT HIGHLIGHTS SPI interface removes the need for parallel conversion and logic traces and reduces general-purpose input/output (GPIO) channel count. Daisy-chain mode removes additional logic traces when multiple devices are used. CRC, invalid read/write address, and SCLK count error detection ensure a robust digital interface. CRC error detection capabilities allow for the use of the ADGS5412 in safety critical systems. Guaranteed break-before-make switching allows the use of the ADGS5412 in multiplexer configurations with external wiring.Trench isolation analog switch section guards against latch-up. A dielectric trench separates the positive (P) and negative (N) channel transistors thereby preventing latch-up even under severe overvoltage conditions.APPLICATIONS Relay replacement Automatic test equipment Data acquisition Instrumentation Avionics Audio and video switching Communication systems

The ADM1272 ?is a hot swap controller that allows a circuit board to be removed from or inserted into a live backplane. It also features current, voltage, and power readback via an integrated 12-bit analog-to-digital converter (ADC), accessed using a PMBus? interface. This device is able to withstand up to 120 V, which makes it very robust in surviving surges and transients commonly associated with high voltage systems, usually clamped using protection devices such as transient voltage suppressors (TVSs) that can often exceed 100 V.The load current, ILOAD, is measured using an internal current sense amplifier that measures the voltage across a sense resistor in the power path via the SENSE+ and SENSE? pins. A default current limit sense voltage of 30 mV is set, but this limit can be?adjusted down, if required, using a resistor divider network from the VCAP regulator output voltage to the ISET pin. An additional resistor can also be placed from ISET to VIN (or VOUT) to allow the current limit to track inversely with the rail voltage. This resistor allows an approximate system power limit to be used.The ADM1272 ?limits the current through the sense resistor by controlling the gate voltage of an external N channel field effect transistor (FET) in the power path. The sense voltage, and therefore the load current, is maintained below the preset maximum. The ADM1272 ?protects the external FET by monitoring and limiting the energy transfer through the FET while the current is being controlled. This energy limit is set by the choice of components connected to the EFAULT pin (for fault protection mode) and the ESTART pin during startup. Therefore, different energy limits can be set for start-up and normal fault conditions. During startup, inrush currents are maintained very low and different areas of the safe operating area (SOA) curve are of interest, whereas during fault conditions, the currents can be much higher.The controller uses the drain to source voltage (VDS) across the FET to set the current profile of the EFAULT and ESTART pins and, therefore, the amount of much energy allowed to be transferred in the FET. This energy limit ensures the MOSFET remains within the SOA limits. Optionally, use a capacitor on the DVDT pin to set the output voltage ramp rate, if required. In case of a short-circuit event, a fast internal overcurrent detector responds in hundreds of ns and signals the gate to shut down. A 1.5 A pull-down device ensures a fast FET response. The gate then recovers control within 50 ?s to ensure minimal disruption during conditions, such as line steps and surges. The?ADM1272 ?features overvoltage (OV) and undervoltage (UV) protection, programmed using external resistor dividers on the UVH, UVL, and OV pins. The use of two pins for undervoltage allows independent accurate rising and falling thresholds. The PWRGD output pin signals when the output voltage is valid and the gate is sufficiently enhanced. The validity of VOUT is determined using the PWGIN pin.The 12-bit ADC measures the voltage across the sense resistor, the supply voltage on the SENSE+ pin, the output voltage, and the temperature using an external NPN/PNP device. A PMBus interface allows a controller to read data from the ADC. As many as 16 unique I2C addresses can be selected, depending on how the two ADRx pins are connected. The?ADM1272 is available in a custom 48-lead LFCSP (7 mm ? 8 mm) with a pinstrap mode that allows the device to be configured for automatic retry or latchoff when an overcurrent (OC) fault occurs.Applications 48 V/54 V systems Servers Power monitoring and control/power budgeting Central office equipment Telecommunication and data communication equipment Industrial applications

The ADM2582E / ADM2587E are fully integrated signal and power isolated data transceivers with ?15 kV ESD protection and are suitable for high speed communication on multipoint transmission lines. The ADM2582E / ADM2587E include an integrated isolated dc-to-dc power supply, which eliminates the need for an external dc-to-dc isolation block.They are designed for balanced transmission lines and comply with ANSI/TIA/EIA-485-A-98 and ISO 8482:1987(E).The devices integrate Analog Devices, Inc., iCoupler? technology to combine a 3-channel isolator, a three-state differential line driver, a differential input receiver, and Analog Devices isoPower dc-to-dc converter into a single package. The devices are powered by a single 5 V or 3.3 V supply, realizing a fully integrated signal and power isolated RS-485 solution.The ADM2582E / ADM2587E driver has an active high enable. An active low receiver enable is also provided that causes the receiver output to enter a high impedance state when disabled.The devices have current limiting and thermal shutdown features to protect against output short circuits and situations where bus contention may cause excessive power dissipation. The parts are fully specified over the industrial temperature range and are available in a highly integrated, 20-lead, wide-body SOIC package.The ADM2582E / ADM2587E contain isoPower technology that uses high frequency switching elements to transfer power through the transformer. Special care must be taken during printed circuit board (PCB) layout to meet emissions standards. Refer to Application Note AN-0971, Control of Radiated Emissions with isoPower Devices, for details on board layout considerations.APPLICATIONSIsolated RS-485/RS-422 interfacesIndustrial field networksMultipoint data transmission systems