The HMC851LC3C is a XOR/XNOR gate function designed to support data transmission rates of up to 28 Gbps, and clock frequencies as high as 28 GHz. The HMC851LC3C also features an output level control pin, VR, which allows for loss compensation or for signal level optimization.All input signals to the HMC851LC3C are terminated with 50 Ohms to ground on-chip, and may be either AC or DC coupled. The differential outputs of the HMC851LC3C may be either AC or DC coupled. Outputs can be connected directly to a 50 Ohm to ground terminated system, while DC blocking capacitors may be used if the terminating system is 50 Ohms to a nonground DC voltage. The HMC851LC3C operates from a single -3.3V DC supply, and is available in a ceramic RoHS compliant 3x3 mm SMT package.APPLICATIONS RF ATE Applications Broadband Test & Measurement Serial Data Transmission?up to 28 Gbps

The HMC789ST89E is a high linearity GaAs InGaP HBT gain block MMIC operating from 0.7 to 2.8 GHz and packaged in an industry standard SOT89 package. Utilizing a minimum number of external components and a single +5V supply, the amplifier output IP3 can be optimized to +45 dBm. The high output IP3 and high gain make the HMC789ST89E ideal for use in PA driver & pre-driver applications in Cellular/4G and Fixed Wireless.Applications Cellular/4G Fixed Wireless & WLAN CATV, Cable Modem & DBS Microwave Radio & Test Equipment IF & RF Applications

The HMC789ST89E is a high linearity GaAs InGaP HBT gain block MMIC operating from 0.7 to 2.8 GHz and packaged in an industry standard SOT89 package. Utilizing a minimum number of external components and a single +5V supply, the amplifier output IP3 can be optimized to +45 dBm. The high output IP3 and high gain make the HMC789ST89E ideal for use in PA driver & pre-driver applications in Cellular/4G and Fixed Wireless.Applications Cellular/4G Fixed Wireless & WLAN CATV, Cable Modem & DBS Microwave Radio & Test Equipment IF & RF Applications

The HMC855LC5 is a 1:4 demultiplexer designed for data deserialization up to 28 Gbps. The device uses both rising and falling edges of the half-rate clock to sample the input data in sequence, D0-D3 and latches the data onto the differential outputs. A quarter-rate clock output generated on chip can be used to clock the data into other devices. The demux is DC coupled supporting broadband operation.All clock and data inputs to the HMC855LC5 are CML and terminated on-chip with 50 Ohms to the positive supply, GND, and may be DC or AC coupled. The differential outputs are source terminated to 50 Ohms and may also be AC or DC coupled. Outputs can be connected directly to a 50 Ohm ground terminated system, or drive devices with CML logic input. The HMC855LC5 also features an output level control pin, VR, which allows for loss compensation or signal level optimization. The HMC855LC5 operates from a single -3.3V supply and is available in RoHS compliant 5x5 mm SMT package.APPLICATIONS SONET OC-192 Broadband Test & Measurement Serial Data Transmission?up to 28 Gbps FPGA Interfacing

The HMC857LC5 is a 2?2 Crosspoint Switch designed to support data transmission rates of up to 14 Gbps and selector port operation up to 14 GHz. The selector routes the differential inputs to either one or both of the desired outputs upon assertion of the appropriately selected port. The HMC857LC5 also features an output level control pin, VR, which allows for loss compensation or for signal level optimization.All single-ended input signals to the HMC857LC5 are terminated with 50 Ohms to ground on-chip, and may be either AC or DC coupled. The outputs of the HMC857LC5 may be operated either differentially or single ended. Outputs can be connected directly to a 50 ??terminated system, while DC blocking capacitors may be used if the terminating system is 50 Ohms to a non-ground DC voltage. The HMC857LC5 operates from a single -3.3V DC supply and is available in a ceramic RoHS compliant 5 נ5 mm SMT package.APPLICATIONS SONET OC-192 and 10 GbE 16G Fiber Channel Network & Storage Dual 2:1 Selector 1:2 Fanout with Input Mux

HMC914LP4E is a limiting amplifier designed to support data transmission rates up to 12.5 Gbps. The amplifier can operate over a wide range of input voltage levels and provides constant-level differential output swing. HMC914LP4E features a loss of signal (LOS) indicator output where the input signal amplitude threshold level can be adjusted using the LOSTH pin. HMC914LP4E also features an output level control pin, VAC, which allows for loss compensation or for output signal level optimization. Differential output signal swing can be adjusted up to 750 mVp-p. An integrated DC offset compensation is also provided on chip. The HMC914LP4E provides an analog RSSI output voltage which is proportional to input signal amplitude.All single-ended input signals are terminated with 50 ohms to +3.3V on-chip, and may be either AC or DC coupled. The outputs of the HMC914LP4E may be operated either differentially or single-ended. The HMC914LP4E operates from a single +3.3V DC supply and is available in a plastic RoHS compliant 4x4 mm SMT package.APPLICATIONS SONET/SDH-Based?Transmission Systems OC-192 Fiber Optic Modules 10 Gigabit Ethernet 8x and 10x Fiber Channel Wideband RF Gain Block

The AD9230 is a 12-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 250 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution. The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.Fabricated on an advanced CMOS process, the AD9230 is available in a 56-lead LFCSP, specified over the industrial temperature range (?40?C to +85?C).PRODUCT HIGHLIGHTS High Performance?Maintains 64.9 dBFS SNR @ 250 MSPS with a 70 MHz input. Low Power?Consumes only 434 mW @ 250 MSPS. Ease of Use?LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample and hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design. Serial Port Control?Standard serial port interface supports various product functions, such as data formatting, disabling the clock duty cycle stabilizer, power-down, gain adjust, and output test pattern generation. Pin-Compatible Family?10-bit pin-compatible family offered as AD9211.APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization

The AD9259 is a quad, 14-bit, 50 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 50 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).The AD9259 is available in a RoHS compliant, 48-lead LFCSP. It is specified over the industrial temperature range of ?40?C to +85?C.PRODUCT HIGHLIGHTSSmall Footprint. Four ADCs are contained in a small, space-saving package.Low power of 98 mW/channel at 50 MSPS.Ease of Use. A data clock output (DCO) operates at frequencies of up to 350 MHz and supports double data rate (DDR) operation.User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements.Pin-Compatible Family. This includes the AD9287 (8-bit), AD9219 (10-bit), and AD9228 (12-bit).APPLICATIONSMedical imaging and nondestructive ultrasoundPortable ultrasound and digital beam-forming systemsQuadrature radio receiversDiversity radio receiversTape drivesOptical networkingTest equipment

The AD9613 is a dual 12-bit, analog-to-digital converter (ADC) with sampling speeds up to 250 MSPS. The AD9613 is designed to support communications applications where low cost, small size, wide bandwidth and versatility are desired.The dual ADC core features a multistage, differential pipelinedarchitecture with integrated output error correction logic. EachADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.The ADC output data are routed directly to the two external 12-bit LVDS output ports and formatted either as interleaved or channel multiplexed.Flexible power-down options allow significant power savings,when desired.Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.The AD9613 is available in a 64-lead LFCSP and is specified overthe industrial temperature range of ?40?C to +85?C.PRODUCT HIGHLIGHTS Integrated dual, 12-bit, 170 MSPS/210 MSPS/250 MSPS ADCs. Fast overrange and threshold detect. Proprietary differential input maintains excellent SNR performance for input frequencies up to 400 MHz. SYNC input allows synchronization of multiple devices. 3-pin, 1.8V SPI port for register programming and register readback. Pin compatibility with the AD9643, allowing a simple migration up to 14 bits, and with the AD6649 and the AD6643.APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications

The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40?C to +85?C industrial temperature range. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm ? 9 mm, 64-lead LFCSP.APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers