The ADP2230 includes two high efficiency, low quiescent current, 800 mA, step-down, dc-to-dc converters in a small, 10-lead, 3 mm ? 3 mm, LFCSP package. The total solution requires only five tiny external components. When the ADP2230 is used with three 0603 capacitors and two 2 mm ? 2 mm inductors, the total solution size is about 48 mm2, resulting in the smallest footprint solution to meet a variety of portable applications. The ADP2230 buck regulator uses a proprietary, high speed, current mode, constant frequency, PWM control scheme for excellent stability and transient response. The buck outputs operate out of phase to reduce the input current ripple. To ensure the longest battery life in portable applications, the ADP2230 has a power saving variable frequency mode that reduces the switching frequency under light load conditions. During logic controlled shutdown, the input is disconnected from the output, and it draws less than 0.1 ?A from the input source. The ADP2230 operates from input voltages from 2.3 V to 6.5 V, allowing the use of multiple alkaline, NiMH, or lithium cells and other standard power sources.The ADP2230 offers multiple options for setting the operating frequency. To maximize light load efficiency, the ADP2230 can operate at a reduced switching frequency in PSM and switch automatically to PWM as the load increases. The ADP2230 can be forced to operate at 2 MHz in PWM only mode when noise considerations are more important than efficiency. The ADP2230 can also be synchronized with a 1.5 MHz to 2.5 MHz external clock via the SYNC pin. When using the external clock synchronization control, both buck outputs operate in phase with the applied clock signal.The ADP2230 includes an internal power switch, synchronous rectifier, and compensation to minimize external part count and maximize efficiency. Other key protection features include undervoltage lockout to prevent deep battery discharge, internal soft start to prevent input current overshoot at startup, and an integrated, switched resistor, QOD function that automatically discharges the output when the device is disabled. Short-circuit protection and thermal overload protection circuits prevent damage in adverse conditions. Applications Portable and battery-powered equipment Automatic meter readers (WSN) Point of sales and transaction processing instruments Mobile phones Digital cameras and audio devices Medical instruments Medium format display tablets and pads

The ADP2325 is a full featured, dual output, step-down dc-to-dcregulator based on a current mode architecture. The ADP2325integrates two high-side power MOSFETs and two low-side driversfor the external N-channel MOSFETs. The two pulse-width modulation(PWM) channels can be configured to deliver dual 5 Aoutputs or a parallel-to-single 10 A output. The regulator operatesfrom input voltages of 4.5 V to 20 V, and the output voltage canbe as low as 0.6 V.The switching frequency can be programmed between 250 kHzand 1.2 MHz, or synchronized to an external clock to minimizeinterference in multirail applications. The dual PWM channelsrun 180? out of phase, thereby reducing input current ripple aswell as reducing the size of the input capacitor.The bidirectional synchronization pin can be programmed ata 60?, 90?, or 120? phase shift, providing the possibility for astackable multiphase power solution.The ADP2325 can be set to operate in pulse frequency modulation(PFM) mode at a light load for higher efficiency or in forcedPWM for noise sensitive applications. External compensationand soft start provide design flexibility. Independent enableinputs and power-good outputs provide reliable power sequencing.To enhance system reliability, the device includes undervoltagelockout (UVLO), overvoltage protection (OVP), overcurrent protection,and thermal shutdown.The ADP2325 operates over the ?40?C to +125?C junctiontemperature range and is available in a 32-lead LFCSP_WQpackage.Applications Communications infrastructure Networking and servers Industrial and instrumentation Healthcare and medical Intermediate power rail conversion

The ADP2370/ADP2371 are high efficiency, low quiescent current, 800 mA buck (step-down) dc-to-dc converters in small 8-lead, 3 mm ? 3 mm LFCSP (QFN) packages. The total solution requires only three tiny external components.The buck regulator uses a proprietary high speed current mode, constant frequency PWM control scheme for excellent stability and transient response. The need for an external rectifier is eliminated by using a high efficiency synchronous rectifier architecture.To ensure the longest battery life in portable applications, the ADP2370/ADP2371 employ a power saving variable frequency mode that reduces the switching frequency under light load conditions. The ADP2370/ADP2371 operate from input voltages of 3.2 V to 15 V allowing the use of multiple alkaline/NiMH, lithium cells, or other standard power sources.The ADP2370/ADP2371 offer multiple options for setting the operational frequency. The ADP2370/ADP2371 can be synchronized to a 600 kHz to 1.2 MHz external clock or it can be forced to operate at 600 kHz or 1.2 MHz via the FSEL pin. The ADP2370/ ADP2371 can be forced to operate in PWM mode (FPWM) when noise considerations are more important than efficiency.A power-good output is available to indicate when the output voltage is below 92% of its nominal value.The ADP2371 is identical to the ADP2370 except that the ADP2371 includes the addition of an integrated switched resistor, quick output discharge function (QOD) that automatically discharges the output when the device is disabled.Both devices include an internal power switch and a synchronous rectifier for minimal external part count and high efficiency. The ADP2370/ADP2371 also include internal soft start and internal compensation for ease of use.During a logic controlled shutdown, the input is disconnected from the output and the regulator draws less than 1.2 ?A from the input source. Other key features include undervoltage lockout to prevent deep battery discharge and soft start to prevent input overcurrent at startup. Short-circuit protection and thermal overload protection circuits prevent damage under adverse conditions.The ADP2370/ADP2371 each use one 0805 capacitor, one 1206 capacitor, and one 4 mm ? 4 mm inductor. The total solution size is about 53 mm2 resulting in a very small footprint solution to meet a variety of portable applications. APPLICATIONS Portable and battery-powered equipment Automatic meter readers (WSN) Point of sales and transaction processing instruments Medical instruments Medium format display tablets and pads

The ADP5062 charger is fully compliant with USB 3.0 and the USB Battery Charging Specification 1.2 and enables charging via the mini USB VBUS pin from a wall charger, car charger, or USB host port.The ADP5062 operates from a 4 V to 6.7 V input voltage range but is tolerant of voltages up to 20 V thereby alleviating concerns about USB bus spikes during disconnect or connect scenarios.The ADP5062 features an internal FET between the linear charger output and the battery. This permits battery isolation and, hence, system powering under a dead battery or no battery scenario, which allows for immediate system function on connection to a USB power supply.Based on the type of USB source, which is detected by an external USB detection chip, the ADP5062 can be set to apply the correct current limit for optimal charging and USB compliance.The ADP5062 has three factory-programmable digital input/out-put pins that provide maximum flexibility for different systems. These digital input/output pins permit combinations of features such as, input current limits, charging enable and disable, charging current limits, and a dedicated interrupt output pin.APPLICATIONS Digital Still Cameras Digital Video Cameras Single Cell Li-Ion Portable Equipment PDAs, Audio and GPS Devices Portable Medical Devices Mobile Phones

The ADRF5042 is a nonreflective SP4T switch manufactured in the silicon on insulator (SOI) process.The ADRF5042 operates from 100 MHz to 44 GHz with an insertion loss of lower than 3.2 dB and an isolation of higher than 35 dB. The device has a RF input power handling capability of 24 dBm for both through and terminated paths.The ADRF5042 requires a dual-supply voltage of +3.3 V and ?3.3 V. The device employs CMOS- and low voltage transistor to transistor logic (LVTTL)-compatible controls.The ADRF5042 has enable and logic select controls to feature all off state and port mirroring, respectively.The ADRF5042 is pin compatible with the ADRF5043 low frequency cutoff version, which operates from 9 kHz to 44 GHz.The ADRF5042 comes in a 24-terminal, 3 mm ? 3 mm, RoHS compliant, land grid array (LGA) package and can operate from ?40?C to +105?C.Applications Industrial Scanners Test instrumentation Cellular infrastructure?millimeterwave (mmWave) 5G Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs)

The ADRF5720 is a silicon, 6-bit digital attenuator with 31.5 dB attenuation control range in 0.5 dB steps.This device operates from 9 kHz to 40 GHz with better than 4.5 dB of insertion loss and excellent attenuation accuracy. The ATTIN port of the ADRF5720 has a radio frequency (RF) input power handling capability of 27 dBm average and 30 dBm peak for all states.The ADRF5720 requires a dual supply voltage of +3.3 V and ?3.3 V. The device features serial peripheral interface (SPI), parallel mode control, and complementary metal-oxide semiconductor (CMOS)-/low voltage transistor to transistor logic (LVTTL)-compatible controls.The ADRF5720 is pin-compatible with the ADRF5730, the fast switching version, which operates from 100 MHz to 40 GHz.The ADRF5720 RF ports are designed to match a characteristic impedance of 50 ?. For wideband applications, impedance matching on the RF transmission lines can further optimize high frequency insertion loss, return loss, and attenuation accuracy characteristics. Refer to the Electrical Specifications section, the Typical Performance Characteristicssection, and the Applications Information section for more details.The ADRF5720 comes in a 24-terminal, 4 mm ? 4 mm, RoHS compliant, land grid array (LGA) package and operates from ?40?C to +105?C.Applications Industrial scanners Test and instrumentation Cellular infrastructure: 5G millimeter wave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs)

The ADRF5740 is a silicon, 4-bit digital attenuator with 22 dB attenuation control range in 2 dB steps.The ADRF5740 operates from 10 MHz to 60 GHz with less than 3.3 dB of insertion loss and with ?(0.2 + 7.0% of attenuation state) of attenuation accuracy at 55 GHz. The ATTIN port of the ADRF5740 has an RF input power handling capability of 24 dBm average and 24 dBm peak for all states.The ADRF5740 requires a dual supply voltage of +3.3 V and ?3.3 V. The ADRF5740 features parallel mode control, and CMOS- and low voltage transistor to transistor logic (LVTTL)-compatible controls.The ADRF5740 RF ports are designed to match a characteristic impedance of 50 ?. The ADRF5740 comes in a 16-terminal, 2.5 mm ? 2.5 mm, RoHS compliant, land grid array (LGA) package and operates from ?40?C to +105?C.Applications Industrial scanners Test and instrumentation Cellular infrastructure: 5G millimeter wave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs)

The ADRV9026 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations. The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs. The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) that provide an array of digital control options are also integrated. To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface. A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9026 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface. The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device. The ADRV9026 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9026 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

The ADRV9029 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations.The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs.The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/ outputs (GPIOs) that provide an array of digital control options are also integrated.To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface.A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9029 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface.This device contains a fully integrated, low power digital predistortion (DPD) adaptation engine for use in power amplifier linearization. DPD enables use of high efficiency power amplifiers, reducing the power consumption of base station radios while also reducing the number of SERDES lanes necessary to interface with baseband processors.The low power crest factor reduction (CFR) engine of the ADRV9029 reduces the peak to average ratio (PAR) of the input signal, enabling higher efficiency transmit line ups while reducing the processing load on baseband processors.The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device.The ADRV9029 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9029 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).APPLICATIONS3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

The ADV3200/ADV3201 are 32 ? 32 analog crosspoint switch matrices. They feature a selectable sync-tip clamp input for ac-coupled applications and an on-screen display (OSD) insertion mux. With ?48 dB of crosstalk and ?80 dB isolation at 5 MHz, the ADV3200/ADV3201 are useful in many high density routing applications. The 0.1 dB flatness out to 60 MHz makes the ADV3200/ADV3201 ideal for composite video switching.The 32 independent output buffers of the ADV3200/ADV3201 can be placed into a high impedance state for paralleling crosspoint outputs so that off-channels present minimal loading to an output bus if building a larger array. The part is available in gain of +1 (ADV3200) or +2 (ADV3201) for ease of use in back-terminated load applications. A single 5 V supply, dual ?2.5 V supplies, or dual ?3.3 V supplies (G = +2) can be used while consuming only 250 mA of idle current with all outputs enabled. The channel switching is performed via a double buffered, serial digital control, which can accommodate daisy chaining of several devices.The ADV3200/ADV3201 are packaged in a 176-lead exposed pad LQFP (24 mm ? 24 mm) and are available over the extended industrial temperature range of ?40?C to +85?C.Applications CCTV surveillance Routing of high speed signals including Composite video (NTSC, PAL, S, SECAM) RGB and component video routing Compressed video (MPEG, Wavelet) Video conferencingData Sheet, Rev. 0, 11/2008