The LTC7001 is a fast high side N-channel MOSFET gate driver that operates from input voltages up to 135V. It contains an internal charge pump that fully enhances an external N-channel MOSFET switch, allowing it to remain on indefinitely.Its powerful driver can easily drive large gate capacitances with very short transition times, making it well suited for both high frequency switching applications or static switch applications that require a fast turn-on and/or turn-off time.The LTC7001 is available in the thermally enhanced 10-lead MSOP package.APPLICATIONS Static Switch Driver Load and Supply Switch Driver Electronic Valve Driver High Frequency High Side Gate Driver

The AD5304/AD5314/AD5324 are quad 8-, 10-, and 12-bit buffered voltage output DACs in 10-lead MSOP and 10-lead LFCSP packages that operate from a single 2.5 V to 5.5 V supply, consuming 500 ?A at 3 V. Their on-chip output amplifiers allow rail-to-rail output swing to be achieved with a slew rate of 0.7 V/?s. A 3-wire serial interface is used; it operates at clock rates up to 30 MHz and is compatible with standard SPI, QSPI, MICROWIRE, and DSP interface standards.The references for the four DACs are derived from one reference pin. The outputs of all DACs can be updated simultaneously using the software LDAC function. The parts incorporate a power-on reset circuit, and ensure that the DAC outputs power up to 0 V and remains there until a valid write takes place to the device. The parts contain a power-down feature that reduces the current consumption of the device to 200 nA @ 5 V (80 nA @ 3 V).The low power consumption of these parts in normal operation makes them ideally suited to portable battery-operated equipment. The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, reducing to 1 ?W in power-down mode.Applications Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators Industrial process controls

TheLTC3623 is a high efficiency, monolithic synchronous buck regulator in which the output voltage is programmed with a single external resistor. The accurate internally generated 50?A current source on the ISET pin allows the user to program an output voltage from 0V to 0.5V below VIN. The user can also directly drive the ISET pin with an external voltage supply to program the converter?s VOUT. The VOUT voltage is fed directly back to the error amplifier to be regulated to the ISET voltage. The operating supply voltage range for the SVIN pin is from 15V down to 4V, while the PVIN pin?s voltage range is 15V down to 1.5V, making it suitable for dual Li-Ion batteries and for taking power from a 12V or 5V rail.The operating frequency is programmable from 400KHz to 4MHz with an external RT resistor. Higher switching frequency allows the use of smaller surface mount inductors while lower frequency allows for higher power efficiency. The unique constant-frequency/controlled on-time architecture is ideal for high step-down ratio applications that are operating at high frequency while demanding fast transient response.Applications Tracking Supply or DDR Memory Supply ASIC Substrate Biasing Point-of-Load (POL) Power Supply Portable Instruments, Battery-Powered Equipment Thermo Electric Cooler (TEC) Systems

Demonstration circuit 2664A is a VCO Rider Board with Loop Filter that supports the popular 0.5" × 0.5" VCO package footprint. The DC2664A expedites evaluation of Phase-Locked Loop (PLL) devices requiring an external Voltage Controlled Oscillator (VCO). Without the DC2664A, each VCO and PLL combination requires a unique loop filter design, resulting in several PLL demo board modifications to evaluate each VCO. These board modifications are time consuming and often result in damage to either the PLL or the VCO. The DC2664A integrates the VCO and loop filter allowing these unique designs to reside on multiple DC2664As. The DC2664A RFOUT and VTUNE SMA connections allow the user to quickly evaluate a PLL with multiple VCOs without risk of damage from multiple board modifications. VCOs are notoriously sensitive to power supply noise and spurs. The DC2664A resolves the concern of locating a low noise and low spurious lab supply by powering the VCO with an onboard ultralow noise and ultrahigh PSRR LDO, the LT3042. A second LT3042 LDO is available on the DC2664A to power an active loop filter. Both LDOs are powered from a single supply, simplifying the number of lab supplies required to evaluate a VCO and PLL combination. The DC2664A was designed to mate directly with the LTC6955 (DC2611A) and LTC6952 (DC2609A) demo boards.

Demonstration circuit 2995A is a buck regulator featuring the LTC7891. The DC2995A operates from a 36V to 72V input voltage range and generates a 12V, 20A output. The LTC7891 has a precision voltage reference which can generate an output voltage with 2% tolerance over the full operating conditions. The 500kHz switching frequency operation results in a small and efficient circuit. The converter achieves over 96% efficiency with 20A load. The demonstration circuit can be easily modified to regulate output voltages from 0.8V to 60V. The DC2995A provides a high performance cost-effective solution for generating a 12V output. The LTC7891 data sheet gives a complete description of this part, its operation and application information and must be read in conjunction with the demo manual.

The AD8340 vector modulator performs arbitrary amplitude and phase modulation of an RF signal. Because the RF signal path is linear, the original modulation is preserved. This part can be used as a general-purpose RF modulator, a variable attenuator/phase shifter, or a remodulator. The amplitude can be controlled from a maximum of ?2 dB to less than ?32 dB, and the phase can be shifted continuously over the entire 360? range. For maximum gain, the AD8340 delivers an OP1dB of 11 dBm, an OIP3 of 24 dBm, and an output noise floor of ?149 dBm/Hz, independent of phase. It operates over a frequency range of 700 MHz to 1.0 GHz.The baseband inputs in Cartesian I and Q format control the amplitude and phase modulation imposed on the RF input signal. Both I and Q inputs are dc-coupled with a ?500 mV differential full-scale range. The maximum modulation band- width is 230 MHz, which can be reduced by adding external capacitors to limit the noise bandwidth on the control lines.Both the RF inputs and outputs can be used differentially or single-ended and must be ac-coupled. The RF input and output impedances are nominally 50 ? over the operating frequency range. The DSOP pin allows the output stage to be disabled quickly to protect subsequent stages from overdrive. The AD8340 operates off supply voltages from 4.75 V to 5.25 V while consuming approximately 130 mA.The AD8340 is fabricated using the Analog Devices, Inc. proprietary, high performance 25 GHz SOI complementary bipolar IC process. It is available in a 24-lead RoHS-compliant LFCSP package and operates over a ?40?C to +85?C temperature range. Evaluation boards are available.APPLICATIONS RF PA linearization/RF predistortion Amplitude and phase modulation Variable attenuators and phase shifters CDMA2000, GSM/EDGE linear power amplifiers Smart antennas

The AD9230 is a 12-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 250 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a complete signal conversion solution. The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are LVDS (ANSI-644) compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing.Fabricated on an advanced CMOS process, the AD9230 is available in a 56-lead LFCSP, specified over the industrial temperature range (?40?C to +85?C).PRODUCT HIGHLIGHTS High Performance?Maintains 64.9 dBFS SNR @ 250 MSPS with a 70 MHz input. Low Power?Consumes only 434 mW @ 250 MSPS. Ease of Use?LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample and hold provide flexibility in system design. Use of a single 1.8 V supply simplifies system power supply design. Serial Port Control?Standard serial port interface supports various product functions, such as data formatting, disabling the clock duty cycle stabilizer, power-down, gain adjust, and output test pattern generation. Pin-Compatible Family?10-bit pin-compatible family offered as AD9211.APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization

The AD9609 is a monolithic, single channel 1.8 V supply, 10-bit,20/40/65/80 MSPS analog-to-digital converter (ADC). It featuresa high performance sample-and-hold circuit and on-chip voltagereference.The product uses multistage differential pipeline architecturewith output error correction logic to provide 10-bit accuracy at80 MSPS data rates and to guarantee no missing codes over thefull operating temperature range.The ADC contains several features designed to maximize flexibilityand minimize system cost, such as programmable clock and dataalignment and programmable digital test pattern generation. Theavailable digital test patterns include built-in deterministic andpseudorandom patterns, along with custom user-defined testpatterns entered via the serial port interface (SPI).A differential clock input with selectable internal 1 to 8 divide ratiocontrols all internal conversion cycles. An optional duty cyclestabilizer (DCS) compensates for wide variations in the clock dutycycle while maintaining excellent overall ADC performance.The digital output data is presented in offset binary, gray code, ortwos complement format. A data output clock (DCO) is providedto ensure proper latch timing with receiving logic. Both 1.8 V and3.3 V CMOS levels are supported.The AD9609 is available in a 32-lead RoHS-compliant LFCSPand is specified over the industrial temperature range (?40?Cto +85?C).APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA Smart antenna systems Battery-powered instruments Handheld scope meters Portable medical imaging Ultrasound Radar/LIDAR PET/SPECT imagingPRODUCT HIGHLIGHTS1. The AD9609 operates from a single 1.8 V analog powersupply and features a separate digital output driver supplyto accommodate 1.8 V to 3.3 V logic families.2. The sample-and-hold circuit maintains excellent performancefor input frequencies up to 200 MHz and is designed for lowcost, low power, and ease of use.3. A standard serial port interface supports various productfeatures and functions, such as data output formatting,internal clock divider, power-down, DCO and data output(D9 to D0) timing and offset adjustments, and voltagereference modes.4. The AD9609 is packaged in a 32-lead RoHS compliantLFCSP that is pin compatible with the AD9629 12-bit ADCand the AD9649 14-bit ADC, enabling a simple migrationpath between 10-bit and 14-bit converters sampling from20 MSPS to 80 MSPS.

The AD9627 is a dual, 12-bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS analog-to-digital converter (ADC). The AD9627 is designed to support communications applications where low cost, small size and versatility are desired.The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The AD9627 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with very short latency. In addition, the programmable threshold detector allows monitoring of the incoming signal power, using the four fast detect bits of the ADC with very low latency. If the input signal level exceeds the programmable threshold, the coarse upper threshold indicator goes high. Because this threshold indicator has very low latency, the user can quickly turn down the system gain to avoid an overrange condition. The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system. The ADC output data can be routed directly to the two external 12-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or 1.8 V LVDS. Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface.The AD9627 is available in a 64-lead LFCSP and is specified over the industrial temperature range of ?40?C to +85?C.PRODUCT HIGHLIGHTS Integrated dual, 12-bit, 80 MSPS/105 MSPS/125 MSPS/150 MSPS ADC. Fast overrange detect and signal monitor with serial output. Signal monitor block with dedicated serial output mode. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 450 MHz. Operation from a single 1.8 V supply and a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode. Pin compatibility with the AD9640, AD9627-11, and AD9600 for a simple migration from 12 bits to 14 bits, 11 bits, or 10 bits.APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) GSM, EDGE, WCDMA, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications

The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40?C to +85?C industrial temperature range. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm ? 9 mm, 64-lead LFCSP.APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers