The ADP8860SHIELD-EVALZ and the ADP8861SHIELD-EVALZ incorporate light emitting diodes (LEDs) for quick and easy evaluation of the ADP8860 and the ADP8861. Note that only the ADP8860SHIELD-EVALZ has dual light intensity sensors. The ADP8860SHIELD-EVALZ and the ADP8861SHIELD-EVALZ follow the form factor of a regular Arduino® shield to allow compatibility with microcontroller boards that use the same interface. These evaluation boards also incorporate a separate header dedicated to I2C communications. The ADP8860 and the ADP8861 are 7-channel LED drivers that utilizes a charge pump with selective gain for maximum efficiency. The LEDs driven by either device are programmable for maximum current and fade in and out times via the I2C interface. Only the ADP8860 has a programable light intensity threshold that can be set via the I2C interface of the device. Each channel can handle up to 30 mA (typical), except for the seventh channel, which can handle 60 mA (typical). Each channel can be unified to have the same fade in time and fade out time, or each channel can have an individual fade in time and fade out time for greater flexibility. For full details on the ADP8860 and the ADP8861, see the ADP8860 and the ADP8861 data sheets, which should be consulted in conjunction with the user guide when using these evaluation boards.

The ADRF5026 is a nonreflective, single-pole, double-throw (SPDT) radio frequency (RF) switch manufactured in a silicon process.The ADRF5026 operates from 100 MHz to 44 GHz with better than 3.8 dB of insertion loss and 45 dB of isolation. The ADRF5026 features an all off control, where both RF ports are in an isolation state. The ADRF5026 has a nonreflective design and both of the RF ports are internally terminated to 50 ?. The ADRF5026 requires a dual-supply voltage of +3.3 V and ?3.3 V. The device employs complimentary metal-oxide semiconductor/low-voltage transistor-transistor logic (CMOS/LVTTL) logic-compatible controls.The ADRF5026 is pin-compatible with the ADRF5027 low frequency cutoff version, which operates from 9 kHz to 44 GHz. The ADRF5026 RF ports are designed to match a characteristic impedance of 50 ?. For ultrawideband products, impedance matching on the RF transmission lines can further optimize high frequency insertion loss and return loss characteristics. Refer to the Narrow-Band Impedance Matching section for an example of a matched circuit that achieves a flat insertion loss response of 2.4 dB from 28 GHz to 43 GHz.The ADRF5026 comes in a 20-terminal, 3 mm ? 3 mm, RoHS-compliant, land grid array (LGA) package and can operate from ?40?C to +105?C.The ADRF5026 supports defense and aerospace applications (AQEC).Applications Industrial scanners Test and instrumentation Cellular infrastructure: 5G mmWave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs)

The ADRV9026 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations. The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs. The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) that provide an array of digital control options are also integrated. To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface. A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9026 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface. The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device. The ADRV9026 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9026 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

The AD9375 is a highly integrated, wideband radio frequency (RF) transceiver offering dual-channel transmitters (Tx) and receivers (Rx), integrated synthesizers, a fully integrated digital predistortion (DPD) actuator and adaptation engine, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption required by 3G/4G small cell and massive multiple input, multiple output (MIMO) equipment in both frequency division duplex (FDD) and time division duplex (TDD) applications. The AD9375 operates from 300 MHz to 6000 MHz, covering most of the licensed and unlicensed cellular bands. The DPD algorithm supports linearization on signal bandwidths up to 40 MHz depending on the power amplifier (PA) characteristics (for example, two adjacent 20 MHz carriers). The IC supports Rx bandwidths up to 100 MHz. It also supports observation receiver (ORx) and Tx synthesis bandwidths up to 250 MHz to accommodate digital correction algorithms.The transceiver consists of wideband direct conversion signal paths with state-of-the-art noise figure and linearity. Each complete Rx and Tx subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digital filters, eliminating the need for these functions in the digital baseband. Several auxiliary functions such as an auxiliary analog-to-digital converter (ADC), auxiliary digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) are integrated to provide additional monitoring and control capability.An ORx channel with two inputs is included to monitor each Tx output and implement calibration applications. This channel also connects to three sniffer receiver (SnRx) inputs that can monitor radio activity in different bands.The high speed JESD204B interface supports lane rates up to 6144 Mbps. Four lanes are dedicated to the transmitters and four lanes are dedicated to the receiver and observation receiver channels.The fully integrated phase-locked loops (PLLs) provide high performance, low power, fractional-N frequency synthesis for the Tx, the Rx, the ORx, and the clock sections. Careful design and layout techniques provide the isolation demanded in high performance base station applications. All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count.The device contains a fully integrated, low power DPD actuator and adaptation engine for use in PA linearization. The DPD feature enables use of high efficiency PAs, significantly reducing the power consumption of small cell base station radios while also reducing the number of JESD204B lanes necessary to interface with baseband processors.A 1.3 V supply is required to power the AD9375 core, and a standard 4-wire serial port controls it. Other voltage supplies provide proper digital interface levels and optimize transmitter and auxiliary converter performance. The AD9375 is packaged in a 12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G small cell base stations (BTS) 3G/4G massive MIMO/active antenna systems

The ADV3202/ADV3203 are 32 ? 16 analog crosspoint switch matrices. They feature a selectable sync-tip clamp input forac-coupled applications and a 2:1 on-screen display (OSD) insertion mux. With ?48 dB of crosstalk and ?80 dB isolationat 5 MHz, the ADV3202/ADV3203 are useful in many high density routing applications. The 0.1 dB flatness out to 60 MHz makes the ADV3202/ADV3203 ideal for both composite and component video switching.The 16 independent output buffers of the ADV3202/ADV3203 can be placed into a high impedance state for paralleling crosspoint outputs so that off-channels present minimal loading to an output bus if building a larger array. The ADV3202 has a gain of +1 while the ADV3203 has a gain of +2 for ease of use in back-terminated load applications. A single +5 V supply, dual ?2.5 V supplies, or dual ?3.3 V supplies can be used while consuming only 195 mA of idle current with all outputs enabled. The channel switching is performed via a double buffered, serial digital control, that can accommodate daisy chaining of several devices.The ADV3202/ADV3203 are packaged in a 176-lead exposed pad LQFP package (24 mm ? 24 mm) and are available over the extended industrial temperature range of ?40?C to +85?C.Applications CCTV surveillance Routing of high speed signals ? ? ? Composite video (NTSC, PAL, S, SECAM) ? ? ? RGB and component video routing ? ? ? Compressed video (MPEG, wavelet) Video conferencingData Sheet, Rev 0, 11/2008

The ADuCM3027/ADuCM3029 microcontroller units (MCUs) are ultra low power microcontroller systems with integrated power management for processing, control, and connectivity. The MCU system is based on the ARM? Cortex?-M3 processor, a collection of digital peripherals, embedded SRAM and flash memory, and an analog subsystem which provides clocking, reset, and power management capability in addition to an analog-to-digital converter (ADC) subsystem. For a feature comparison across the ADuCM3027/ADuCM3029 product offerings, see Table 1. Table 1. Product Flash Memory Options Device Embedded Flash Memory Size ADuCM3029 256 kB ADuCM3027 128 kB System features that are common across the ADuCM3027/ADuCM3029/ADuCM3029-1/ADuCM3029-2 MCUs include the following: Up to 26 MHz ARM Cortex-M3 processor Up to 256 kB of embedded flash memory with error correction code (ECC) Optional 4 kB cache for lower active power 64 kB system SRAM with parity Power management unit (PMU) Multilayer advanced microcontroller bus architecture (AMBA) bus matrix Central direct memory access (DMA) controller Beeper interface Serial port (SPORT), serial peripheral interface (SPI), inter-integrated circuit (I2C), and universal asynchronous receiver/transmitter (UART) peripheral interfaces Cryptographic hardware support with advanced encryption standard (AES) and secure hash algorithm (SHA)-256 Real-time clock (RTC) General-purpose and watchdog timers Programmable general-purpose input/output (GPIO) pins Hardware cyclic redundancy check (CRC) calculator with programmable generator polynomial Power-on reset (POR) and power supply monitor (PSM) 12-bit successive approximation register (SAR) ADC True random number generator (TRNG)To support low dynamic and hibernate power management, the ADuCM3027/ADuCM3029 MCUs provide a collection of power modes and features, such as dynamic and software controlled clock gating and power gating.The ADuCM3029-1 and ADuCM3029-2 MCU models share the same features and functionality as that of the ADuCM3029 MCU. All specifications pertaining to the ADuCM3027 and ADuCM3029 are also applicable to the ADuCM3029-1 and ADuCM3029-2.For full details on the ADuCM3027/ADuCM3029 MCUs, refer to the ADuCM302x Ultra Low Power ARM Cortex-M3 MCU with Integrated Power Management Hardware Reference Manual.Product Highlights Industry leading ultralow power consumption. Robust operation, including full voltage monitoring in deep sleep modes, ECC support on flash, and parity error detection on SRAM memory. Leading edge security. Fast encryption provides read protection to customer algorithms. Write protection prevents device reprogramming by unauthorized code. Failure detection of 32 kHz LFXTAL via interrupt. SensorStrobe? for precise time synchronized sampling of external sensors. Works in hibernate mode, resulting in drastic current reduction in system solutions. Current consumption reduces by 10 times when using, for example, the ADXL363 accelerometer. Software intervention is not required after setup. No pulse drift due to software execution.Applications Internet of Things (IoT) Electronic shelf label (ESL) and signage Smart infrastructure Smart lock Asset tracking Smart machine, smart metering, smart building, smart city, and smart agriculture Wearables Fitness and clinical Machine learning and neural network?

Demonstration circuit SCP-LT1962-EVALZ is a 20V, 300mA Low Dropout (LDO) regulator designed to allow low noise operation in noise sensitive circuits. It is easily configured for a wide output range and can provide extremely quiet operation with its high PSRR. Like all boards in the Signal Chain Power series, this board is designed to be easily plugged into other SCP boards to form a complete signal chain power system, enabling fast evaluation of low power signal chains. To evaluate this board, some universal SCP hardware is required, namely: SCP-INPUT-EVALZ SCP-OUTPUT-EVALZ SCP-1X5BKOUT-EVALZ SCP-THRUBRD-EVALZ SCP-FILTER-EVALZ SCP-1X2BKOUT-EVALZ SCP-5X1-EVALZ   To properly evaluate SCP series demo boards, you will need the SCP Configurator companion software. SCP Configurator can help you choose the right board and topology for your design. Note that the Demo Manual does not cover details important to the operation and configuration regarding the LT1962. Please refer to the LT1962 data sheet for a complete description of the part.

Supervisor Open Drain or Open Collector 1 Channel SC-70-3

Demonstration circuit 1244 is a Low Quiescent Current, Dual Output Synchronous Buck Converter featuring the LTC3890EGN-1. DC1244 converts a 4.5V to 60V voltage source to 3.3V at 5.0A and 8.5V at 3.0A. When the input voltage is close to or below 9V, the 8.5V output enters dropout mode.The "-1" version has a fixed current limit and current foldback. See data sheet for other differences.

Demonstration circuit DC1256A is a single-battery standalone battery charger that can support any version ofthe LTC4012 family of parts. The LTC4012 family of charge controller IC’s do not support charge termination for any specific battery chemistry. Any charger termination, if necessary, is accomplished outside the LTC4012 with the most common method using a microcontroller. The DC1256A is shipped with the LTC4012-2 installed,which is optimized for Li-ion charge applications using a 4.2V/cell float voltage.The charger output voltage is programmed by jumpers to support 1, 2, 3 and 4 series stack Li-ion batteries. The input voltage is can be between 6V and 20V with the maximum voltage of the Demo Board design limited by the input capacitor voltage ratings. To reach full charge,the minimum input voltage must be greater than the float voltage setting.