The ADM1186-1 and ADM1186-2 are integrated, four-channel, voltage monitoring and sequencing devices. A 2.7 V to 5.5 V power supply is required on the VCC pin for power.Four precision comparators monitor four voltage rails, with all comparators sharing a 0.6 V reference and a worst-case accuracy of 0.8%. Resistor networks that are external to the VIN1, VIN2, VIN3, and VIN4 pins set the Under Voltage (UV) trip points for the monitored supply rails.The ADM1186-1 and ADM1186-2 have four open drain enable outputs, OUTx, that are used to enable power supplies. An open drain power good output, PWRGD, is provided that indicatesthe four VINx inputs are above their UV thresholds.A state machine monitors the state of the UP and?DOWN pins on the ADM1186-1 or the UP/overbar: DOWN pin on the ADM1186-2 to control the supply sequencing direction. In the ?Wait Start?state, a rising edge transition on the UP or UP/DOWN pin triggers a power-up sequence. A falling edge transition on the DOWN or UP/DOWN pin in the ?Power Up Done? statetriggers a power down sequence.During a power up sequence, the state machine enables each power supply in turn. The supply output voltage is monitored to determine if it rises above the UV threshold level within a userdefined duration called the blanking time. If a supply rises above the UV threshold then the next enable output in the sequence is turned on. In addition to the blanking time a user may also define sequencing time delays between each enable output turning on. When all four enable outputs are on, and the four VINx pins are above their UV trip points the power up sequence is complete. The ADM1186-1 provides an open drain pin, SEQ_DONE, that is asserted high to provide an indication that an up sequence is complete. The SEQ_DONE pins is allows multiple cascadedADM1186-1 devices to be perform controlled power up and down sequences. During a power down sequence the enable outputs turn off inreverse order. The sequence time delays between successive supplies the same as during the power up sequence, and no blanking time is used during a power down sequence. At the end of a down sequence the SEQ_DONE pin is brought low. During sequencing and when powered up, the state machine continuously monitors for any fault conditions. Faults include a UV condition on any of the inputs, or an unexpected controlinput. Any fault that occurs causes the state machine to enter a fault handler. This immediately turns off all enable outputs, and ensures that the device is ready to start a new up sequence. The ADM1186-1 has a bi-directional open drain pin, FAULT, that facilitates fault handling when using multiple devices. An ADM1186-1 experiencing a fault condition drives the FAULT pin low, causing other connected ADM1186-1devices to enter their own fault handling state.The ADM1186-1 is available in a 20-lead QSOP package andthe ADM1186-2 is available in a 16-lead QSOP package.

The ADM1275 is a hot-swap controller that allows a circuit board to be removed from or inserted into a live backplane. It also features current and voltage readback via an integrated 12-bit analog-to-digital converter (ADC), accessed using a PMBus? interface. The load current is measured using an internal current sense amplifier that measures the voltage across a sense resistor in the power path via the SENSE+ and SENSE? pins. A default limit of 20 mV is set, but this limit can be adjusted, if required, using a resistor divider network from the internal reference voltage to the ISET pin.The ADM1275 limits the current through the sense resistor by controlling the gate voltage of an external N-channel FET in the power path, via the GATE pin. The sense voltage?and, therefore, the load current?is maintained below the preset maximum. The ADM1275 protects the external FET by limiting the time that the FET remains on while the current is at its maximum value. This current limit time is set by the choice of capacitor connected to the TIMER pin. In addition, a foldback resistor network can be used to actively lower the current limit as the voltage across the FET is increased. This helps to maintain constant power in the FET and allows the safe operating area (SOA) to be adhered to in an effective manner.In case of a short-circuit event, a fast internal overcurrent detector responds within 370 ns and signals the gate to shut down. A 1500 mA pull-down device ensures a fast FET response. The ADM1275 features overvoltage and undervoltage protection, programmed using external resistor dividers on the UV and OV pins. A PWRGD signal can be used to detect when the output supply is valid, using the FLB pin to monitor the output. GPO pins can be configured as various output signals that can be asserted when a programmed current or voltage level is reached.The 12-bit ADC can measure the current in the sense resistor, as well as the supply voltage on the SENSE+ pin or the output voltage. A PMBus interface allows a controller to read current and voltage data from the ADC. Measurements can be initiated by a PMBus command. Alternatively, the ADC can run continuously, and the user can read the latest conversion data whenever required. Up to four unique PMBus addresses can be selected, depending on the way that the ADR pin is connected. The ADM1275-1 and ADM1275-3 are available in a 20-lead QSOP and 20-lead LFCSP and have a LATCH pin that can be configured for automatic retry or latch-off when an overcurrent fault occurs. The ADM1275-2 is available in a 16-lead QSOP with latch-off mode only.Applications Power monitoring and control/power budgeting Central office equipment Telecommunication and data communication equipment PCs/servers

The ADM1276 is a hot swap controller that allows a circuit board to be removed from or inserted into a live backplane. It also features current and voltage readback via an integrated 12-bit analog-to-digital converter (ADC), accessed using a PMBus? interface.The load current is measured using an internal current sense amplifier that measures the voltage across a sense resistor in the power path via the SENSE+ and SENSE? pins. A default limit of 20 mV is set, but this limit can be adjusted, if required, using a resistor divider network from the internal reference voltage to the ISET pin.The ADM1276 limits the current through the sense resistor by controlling the gate voltage of an external N-channel FET in the power path, via the GATE pin. The sense voltage--and, therefore, the load current--is maintained below the preset maximum. The ADM1276 protects the external FET by limiting the time that the FET remains on while the current is at its maximum value. This current-limit time is set by the choice of capacitor connected to the TIMER pin. In addition, a foldback resistor network can be used to actively lower the current limit as the voltage across the FET is increased. This helps to maintain constant power in the FET and allows the safe operating area (SOA) to be adhered to in an effective manner.In case of a short-circuit event, a fast internal overcurrent detector responds within 370 ns and signals the gate to shut down. A 1500 mA pull-down device ensures a fast FET response. The ADM1276 features overvoltage (OV) and undervoltage (UV) protection, programmed using external resistor dividers on the UV and OV pins. A PWRGD signal can be used to detect when the output supply is valid, using the FLB pin to monitor the output. GPO pins can be configured as various output signals that can be asserted when a programmed current or voltage level is reached.The 12-bit ADC can measure the current in the sense resistor, as well as the supply voltage on the SENSE+ pin or the output voltage. A PMBus interface allows a controller to read current and voltage data from the ADC. Measurements can be initiated by a PMBus command. Alternatively, the ADC can run continuously, and the user can read the latest conversion data whenever required. As many as four unique PMBus addresses can be selected, depending on the way that the ADR pin is connected.The ADM1276 is available in a 20-lead LFCSP and has a LATCH pin that can be configured for automatic retry or latch-off when an overcurrent fault occurs.APPLICATIONS Power monitoring and control/power budgeting Central office equipment Telecommunication and data communication equipment PCs/servers

The ADM2461E/ADM2463E are 500 kbps, 5.7 kV rms, signal isolated RS-485 transceivers that pass radiated emissions testing to the EN55032 Class B standard with margin on a 2-layer printed circuit board (PCB). The ADM2461E/ADM2463E isolation barrier provides robust immunity to noise and system level EMC events. The devices are protected against ??12 kV contact and ? ?15 kV air IEC61000-4-2 electrostatic discharge (ESD) events on the RS-485 A, B, Y, and Z pins. The devices feature cable invert pins to allow quick correction of the reversed cable connection on the A, B, Y, and Z bus pins while maintaining full receiver fail-safe performance.?These devices are optimized for low speed over long cable runs and have a maximum data rate of 500 kbps. The high differential output voltage makes these devices suitable for Profibus nodes when powered with 5 V on the VDD2 supply. The VDD1 primary supply and VDD2 isolated supply both support a wide range of voltages (1.7 V to 5.5 V and 3 V to 5.5 V, respectively). Half-duplex and full duplex device options are available in the industry standard 16-lead, wide-body, standard SOIC_W package with >8.0 mm creepage and clearance.?APPLICATIONS?? Heating, ventilation, and air conditioning (HVAC) networks Industrial field buses Building automation Utility networks

The ADM2490E is an isolated data transceiver with ?8 kV ESD protection that is suitable for high speed, full-duplex communication on multipoint transmission lines. It is designed for balanced transmission lines and complies with ANSI TIA/EIA-485-A-1998 and ISO 8482: 1987(E). The device employs Analog Devices, Inc., iCoupler? technology to combine a 2-channel isolator, a three-state differential line driver, and a differential input receiver into a single package.The differential transmitter outputs and receiver inputs feature electrostatic discharge circuitry that provides protection to ?8 kV using the human body model (HBM). The logic side of the device can be powered with either a 5 V or a 3 V supply, whereas the bus side requires an isolated 5 V supply.The device has current-limiting and thermal shutdown features to protect against output short circuits and situations where bus contention could cause excessive power dissipation.The ADM2490E is available in a wide body, 16-lead SOIC package and operates over the ?40?C to +105?C temperature range.Applications Isolated RS-485/RS-422 Interfaces Industrial Field Networks INTERBUS Multipoint Data Transmission Systems

The ADM4168E is a dual RS-422 transceiver suitable for high speed communication on point to point and multidrop transmission lines. The ADM4168E is designed for balanced transmission lines and complies with TIA/EIA-422-B. The differential driver outputs and receiver inputs feature electrostatic discharge (ESD) circuitry that provides protection up to ?15 kV human body model (HBM) and ?8 kV IEC 61000-4-2 (contact and air discharge). The ADM4168E operates from a single 5 V power supply. Excessive power dissipation caused by bus contention or output shorting is prevented by short-circuit protection circuitry. Short-circuit protection circuits limit the maximum output current to ?150 mA during fault conditions. The receivers of the ADM4168E contain a fail-safe feature that results in a logic high output state if the inputs are unconnected (floating). The ADM4168E is fully specified over the commercial and industrial temperature ranges and is available in a 16-lead TSSOP package.Applications RS-422 interfaces High data rate motor control Single-ended to differential signal conversion Point to point and multidrop transmission systems

The ADN4650/ADN4651/ADN46521 are signal isolated, low voltage differential signaling (LVDS) buffers that operate at up to 600 Mbps with very low jitter.The devices integrate Analog Devices, Inc., iCoupler? technology, enhanced for high speed operation, to provide galvanic isolation of the TIA/EIA-644-A compliant LVDS drivers and receivers. This technology allows drop-in isolation of an LVDS signal chain.Multiple channel configurations are offered, and the LVDS receivers on the ADN4651/ADN4652 include a fail-safe mechanism to ensure a Logic 1 on the corresponding LVDS driver output when the inputs are floating, shorted, or terminated, but not driven.For high speed operation with low jitter, the LVDS and isolator circuits rely on a 2.5 V supply. An integrated on-chip low dropout regulator (LDO) can provide the required 2.5 V from an external 3.3 V power supply. The devices are fully specified over a wide industrial temperature range and are available in a 20-lead, wide body SOIC package with 5 kV rms isolation or a 20-lead SSOP package with 3.75 kV rms isolation.Applications Analog front-end (AFE) isolation Data plane isolation Isolated high speed clock and data links Isolated serial peripheral interface (SPI) over LVDS

The ADN4654/ADN4655/ADN46561? are signal isolated, low voltage differential signaling (LVDS) buffers that operate at up to 1.1 Gbps with low jitter. The devices integrate Analog Devices, Inc., iCoupler? technology, enhanced for high speed operation to provide galvanic isolation of the TIA/EIA-644-A compliant LVDS drivers and receivers. This integration allows drop-in isolation of an LVDS signal chain.The ADN4654/ADN4655/ADN4656 comprise multiple channel configurations, and the LVDS receivers on the ADN4655 and ADN4656 include a fail-safe mechanism to ensure a Logic 1 on the corresponding LVDS driver output when the inputs are floating, shorted, or terminated but not driven.For high speed operation with low jitter, the LVDS and isolator circuits rely on a 2.5 V supply. An integrated on-chip low dropout (LDO) regulator can provide the required 2.5 V from an external 3.3 V power supply. The devices are fully specified over a wide industrial temperature range and come in a 20-lead, wide body SOIC_W package with 5 kV rms isolation or in a 20-lead SSOP package with 3.75 kV rms isolation.Applications Isolated video and imaging data Analog front-end isolation Data plane isolation Isolated high speed clock and data links1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.

The EVAL-ADPD2140Z evaluation kit allows users to interface with the ADPD2140 infrared (IR) light angle sensor, collect data from the ADPD2140, and evaluate gesture recognition and triangulation capabilities. The evaluation kit requires the EVAL-ADPDM3Z evaluation board and the Applications Wavetool, a graphical user interface (GUI) that provides users with low level and high level config-urability, real-time data analysis, and user datagram protocol (UDP) transfer capability, which allows the EVAL-ADPDM3Z evaluation board to interface to a PC. The Applications Wavetool can be downloaded from the EVAL-ADPD2140Z evaluation board product page. The USB port of the PC powers the EVAL-ADPDM3Z evaluation board and provides power to the EVAL-ADPD2140Z evaluation board. On-board voltage regulators provide voltage supplies for the ADPD2140. The EVAL-ADPD2140Z evaluation board schematic indicates signal names for easy identification. Full specifications for the ADPD2140 are available in the ADPD2140 data sheet, which should be consulted in conjunction with this user guide when working with the EVAL-ADPD2140Z evaluation board.

The ADRF6755 is a highly integrated quadrature modulator, frequency synthesizer, and programmable attenuator. The device covers an operating frequency range from 100 MHz to 2400 MHz for use in satellite, cellular, and broadband communications.The ADRF6755 modulator includes a high modulus, fractional-N frequency synthesizer with integrated VCO, providing less than 1 Hz frequency resolution, and a 47 dB digitally controlled output attenuator with 1 dB steps.Control of all the on-chip registers is through a user-selected SPI interface or I2C interface. The device operates from a single power supply ranging from 4.75 V to 5.25 V.