Reaching speeds of up to 1 GHz, the ADSP-2159x processors are members of the SHARC? family of products. The ADSP-2159x processor is a dual-SHARC+? core DSP that doubles the audio performance of its single-SHARC+ core ADSP-2156x predecessor while maintaining pin-compatibility to it in the BGA package, providing design scalability from 400 MHz (ADSP-21566) to 2 GHz (ADSP-21593).The ADSP-2159x SHARC processors are members of the SIMD SHARC family of digital signal processors (DSPs) that feature Analog Devices, Inc., Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with large on-chip static random-access memory (SRAM), multiple internal buses that eliminate input/output (I/O) bottlenecks, and innovative digital audio interfaces (DAI). New additions to the SHARC+ core include cache enhancements and branch prediction, while maintaining instruction set compatibility to previous SHARC products.By integrating a rich set of industry-leading system peripherals and memory (see Table 1 in the data sheet), the SHARC+ processor is the platform of choice for applications that require programmability similar to reduced instruction set computing (RISC), multimedia support, and leading edge signal processing in one integrated package. These applications span a wide array of markets, including automotive, professional audio, and industrial-based applications that require high floating-point performance.APPLICATIONS Automotive: audio amplifier, head unit, ANC/RNC, rear seat entertainment, digital cockpit, ADAS Consumer & Professional Audio: speakers, sound bars, AVRs, conferencing systems, mixing consoles, microphone arrays, headphones

The ADF4193 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations. It consists of a low noise, digital phase frequency detector (PFD), and a precision differential charge pump. There is also a differential amplifier to convert the differential charge pump output to a single-ended voltage for the external voltage-controlled oscillator (VCO).The ?-?-based fractional interpolator, working with the N divider, allows programmable modulus fractional-N division. Additionally, the 4-bit reference (R) counter and on-chip frequency doubler allow selectable reference signal (REFIN) frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles inside the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases cost, complexity, PCB area, shielding, and characterization on previous ping-pong GSM PLL architectures.Applications GSM/EDGE base stations PHS base stations Instrumentation and test equipment

The LT5511 mixer is designed to meet the high linearity requirements of cable TV infrastructure downstream transmitters and wireless infrastructure transmit systems. The IC includes a differential LO buffer amplifier driving a double-balanced mixer. The LO, RF and IF ports can be easily matched to a broad range of frequencies for different applications. The high performance capability of the LO buffer allows the use of a single-ended source, thus eliminating the need for an LO balun.The LT5511 mixer delivers +17dBm typical input 3rd order intercept point at 950MHz, and +15.5dBm IIP3 at 1900MHz, with IF input signal levels of ? 5dBm. The input 1dB compression point is typically +6dBm.Applications CATV Downlink Infrastructure Wireless Infrastructure High Linearity Mixer Applications

The LT8550 is a multiphase expander for synchronous buck DC/DC converters. It operates in tandem with any buck DC/DC converter to increase the load current capability by adding additional phases, which are clocked outof-phase to reduce ripple current and filtering capacitance. It easily adds phases without the need to route sensitive feedback and control signals. The LT8550 integrates gate drivers and can support up to four buck phases per device. Multiple LT8550?s can be used for up to 18 phases. It accurately monitors and adjusts the current of each channel to achieve excellent DC and transient current sharing. The LT8550 operates over a fixed frequency from 100kHz to 1MHz, or can be synchronized to an external clock.??Applications?? High Current Distributed Power Systems Telecom, Datacom, and Storage Systems Industrial and Automotive

DC271A: Demo Board for the LTC1628 High Efficiency, 2-Phase Synchronous Step-Down Switching Regulator.

Demonstration circuit 1270A is a low input voltage, high efficiency synchronous buck DC/DC controller that features the LTC3852EUDD. With a 2.7V to 5.5V input range. It can supply 15A maximum load current at 1.5V output. The integrated charge pump provides 5V to the LTC3852’s control logic and gate drives, supporting a wide selection of logic-level N-channel power MOSFETs with high efficiency.

MSP-TS430DA38 - 38-pin Target Development Board for MSP430F2x and MSP430G2x MCUs

TLV320AIC3107 Evaluation Module and USB Motherboard

Evaluation Board, STM32F469NI MCU, SPI/I2C Interfaces, Integrated ST-LINK/V2-1 Debugger

Evaluation Module for Battery Charge Management IC