The ADRF5019 is a nonreflective, single pole, double throw (SPDT) RF switch manufactured in a silicon process.The ADRF5019 operates from 100 MHz to 13 GHz with better than 0.8 dB insertion loss and 45 dB of isolation at 8 GHz. TheADRF5019 has a nonreflective design, and the RF ports are internally terminated to 50 ?.The ADRF5019 switch requires a dual supply voltage of +3.3 V and ?2.5 V and positive control voltage inputs. This switchemploys complementary metal-oxide semiconductor (CMOS)-compatible and low voltage transistor transistor logic (LVTTL)-compatible controls.The ADRF5019 can also operate with a single positive supply voltage (VDD) applied. The negative supply voltage (VSS) is tiedto ground. Even in single-supply operation mode, the ADRF5019 can cover the 100 MHz to 13 GHz operating frequency andmaintain good power handling performance. See the Applications Information section for more details.The ADRF5019 is pin-compatible with the HMC1118, the low frequency cutoff version, which operates from 9 kHz to 13.0 GHz.The ADRF5019 comes in a 16-lead, lead frame chip scale package (LFCSP) and operates from ?40?C to +105?C.Applications Test instrumentation Microwave radios and very small aperture terminals (VSATs) Military radios, radars, and electronic counter measures (ECMs) Fiber optics and broadband telecommunications

The ADRF5040 is a general-purpose, broadband high isolation, nonreflective single-pole, quad-throw (SP4T) switch in an LFCSP surface-mount package. Covering the 9 kHz to 12.0 GHz range, the switch offers high isolation and low insertion loss. The switch features 34 dB isolation and 0.8 dB insertion loss up to 8.0 GHz, and a 9 ?s settling time of 0.05 dB margin of the final radio frequency output (RFOUT). The switch operates using positive control voltage of 3.3 V and 0 V and requires +3.3 V and ?3.3 V supplies. The ADRF5040 is packaged in a 4 mm ? 4 mm, surface-mount LFCSP package.Applications Test instrumentation Microwave radios and very small aperture terminals (VSATs) Military radios, radars, and electronic counter measures (ECMs) Fiber optics and broadband telecommunications?

The ADRF5042 is a nonreflective SP4T switch manufactured in the silicon on insulator (SOI) process.The ADRF5042 operates from 100 MHz to 44 GHz with an insertion loss of lower than 3.2 dB and an isolation of higher than 35 dB. The device has a RF input power handling capability of 24 dBm for both through and terminated paths.The ADRF5042 requires a dual-supply voltage of +3.3 V and ?3.3 V. The device employs CMOS- and low voltage transistor to transistor logic (LVTTL)-compatible controls.The ADRF5042 has enable and logic select controls to feature all off state and port mirroring, respectively.The ADRF5042 is pin compatible with the ADRF5043 low frequency cutoff version, which operates from 9 kHz to 44 GHz.The ADRF5042 comes in a 24-terminal, 3 mm ? 3 mm, RoHS compliant, land grid array (LGA) package and can operate from ?40?C to +105?C.Applications Industrial Scanners Test instrumentation Cellular infrastructure?millimeterwave (mmWave) 5G Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs)

The ADRF5519 is a dual-channel, integrated RF, front-end multichip module designed for time division duplexing (TDD) applications that operates from 2.3 GHz to 2.8 GHz. The ADRF5519 is configured in dual channels with a cascading two stage low noise amplifier (LNA) and a high power silicon single pole, double-throw (SPDT) switch.In high gain mode, the cascaded two-stage LNA and switch offer a low noise figure (NF) of 1.0 dB and a high gain of 35 dB at 2.6 GHz with an output third-order intercept point (OIP3) of 32 dBm (typical). In low gain mode, one stage of the two-stage LNA is in bypass, providing 14 dB of gain at a lower current of 36 mA. In power-down mode, the LNAs are turned off and the device draws 12 mA.In transmit operation, RF inputs are connected to a termination pin (ANT-CHA or ANT-CHB connected to TERM-CHA or TERM-CHB, respectively). The switch provides a low insertion loss of 0.5 dB and handles a long-term evolution (LTE) average power (9 dB peak to average ratio (PAR)) of 43 dBm for full lifetime operation.The device comes in a RoHS-compliant, compact, 6 mm ? 6 mm, 40-lead LFCSP package.APPLICATIONSWireless infrastructureTDD massive multiple input and multiple output and active antenna systemsTDD-based communication systems

The ADRF5545A is a dual-channel, integrated radio frequency (RF), front-end multichip module designed for time division duplexing (TDD) applications that operates from 2.4 GHz to 4.2 GHz. The ADRF5545A is configured in dual channels with a cascading two-stage low noise amplifier (LNA) and a high power silicon single-pole, double-throw (SPDT) switch.In high gain mode, the cascaded two-stage LNA and switch offer a low noise figure (NF) of 1.45 dB and a high gain of 32 dB at 3.6 GHz with an output third-order intercept point (OIP3) of 32 dBm (typical). In low gain mode, one stage of the two-stage LNA is in bypass, providing 16 dB of gain at a lower current of 36 mA. In power-down mode, the LNAs are turned off and the device draws 12 mA.In transmit operation, when RF inputs are connected to a termination pin (TERM-ChA or TERM-ChB), the switch provides a low insertion loss of 0.65 dB and handles long-term evolution (LTE) average power (9 dB peak to average ratio (PAR)) of 40 dBm for full lifetime operation and 43 dBm for single event (<10 sec) LNA protection operation.The device comes in an RoHS compliant, compact, 6 mm ? 6 mm, 40-lead LFCSP package.Applications Wireless infrastructure TDD massive multiple input and multiple output and active antenna systems TDD-based communication systems

The ADRF5720 is a silicon, 6-bit digital attenuator with 31.5 dB attenuation control range in 0.5 dB steps.This device operates from 9 kHz to 40 GHz with better than 4.5 dB of insertion loss and excellent attenuation accuracy. The ATTIN port of the ADRF5720 has a radio frequency (RF) input power handling capability of 27 dBm average and 30 dBm peak for all states.The ADRF5720 requires a dual supply voltage of +3.3 V and ?3.3 V. The device features serial peripheral interface (SPI), parallel mode control, and complementary metal-oxide semiconductor (CMOS)-/low voltage transistor to transistor logic (LVTTL)-compatible controls.The ADRF5720 is pin-compatible with the ADRF5730, the fast switching version, which operates from 100 MHz to 40 GHz.The ADRF5720 RF ports are designed to match a characteristic impedance of 50 ?. For wideband applications, impedance matching on the RF transmission lines can further optimize high frequency insertion loss, return loss, and attenuation accuracy characteristics. Refer to the Electrical Specifications section, the Typical Performance Characteristicssection, and the Applications Information section for more details.The ADRF5720 comes in a 24-terminal, 4 mm ? 4 mm, RoHS compliant, land grid array (LGA) package and operates from ?40?C to +105?C.Applications Industrial scanners Test and instrumentation Cellular infrastructure: 5G millimeter wave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs)

The ADRF5740 is a silicon, 4-bit digital attenuator with 22 dB attenuation control range in 2 dB steps.The ADRF5740 operates from 10 MHz to 60 GHz with less than 3.3 dB of insertion loss and with ?(0.2 + 7.0% of attenuation state) of attenuation accuracy at 55 GHz. The ATTIN port of the ADRF5740 has an RF input power handling capability of 24 dBm average and 24 dBm peak for all states.The ADRF5740 requires a dual supply voltage of +3.3 V and ?3.3 V. The ADRF5740 features parallel mode control, and CMOS- and low voltage transistor to transistor logic (LVTTL)-compatible controls.The ADRF5740 RF ports are designed to match a characteristic impedance of 50 ?. The ADRF5740 comes in a 16-terminal, 2.5 mm ? 2.5 mm, RoHS compliant, land grid array (LGA) package and operates from ?40?C to +105?C.Applications Industrial scanners Test and instrumentation Cellular infrastructure: 5G millimeter wave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs)

The ADRV9026 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations. The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs. The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) that provide an array of digital control options are also integrated. To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface. A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9026 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface. The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device. The ADRV9026 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9026 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

The ADRV9029 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations.The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs.The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/ outputs (GPIOs) that provide an array of digital control options are also integrated.To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface.A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9029 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface.This device contains a fully integrated, low power digital predistortion (DPD) adaptation engine for use in power amplifier linearization. DPD enables use of high efficiency power amplifiers, reducing the power consumption of base station radios while also reducing the number of SERDES lanes necessary to interface with baseband processors.The low power crest factor reduction (CFR) engine of the ADRV9029 reduces the peak to average ratio (PAR) of the input signal, enabling higher efficiency transmit line ups while reducing the processing load on baseband processors.The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device.The ADRV9029 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9029 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).APPLICATIONS3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

The ADV3200/ADV3201 are 32 ? 32 analog crosspoint switch matrices. They feature a selectable sync-tip clamp input for ac-coupled applications and an on-screen display (OSD) insertion mux. With ?48 dB of crosstalk and ?80 dB isolation at 5 MHz, the ADV3200/ADV3201 are useful in many high density routing applications. The 0.1 dB flatness out to 60 MHz makes the ADV3200/ADV3201 ideal for composite video switching.The 32 independent output buffers of the ADV3200/ADV3201 can be placed into a high impedance state for paralleling crosspoint outputs so that off-channels present minimal loading to an output bus if building a larger array. The part is available in gain of +1 (ADV3200) or +2 (ADV3201) for ease of use in back-terminated load applications. A single 5 V supply, dual ?2.5 V supplies, or dual ?3.3 V supplies (G = +2) can be used while consuming only 250 mA of idle current with all outputs enabled. The channel switching is performed via a double buffered, serial digital control, which can accommodate daisy chaining of several devices.The ADV3200/ADV3201 are packaged in a 176-lead exposed pad LQFP (24 mm ? 24 mm) and are available over the extended industrial temperature range of ?40?C to +85?C.Applications CCTV surveillance Routing of high speed signals including Composite video (NTSC, PAL, S, SECAM) RGB and component video routing Compressed video (MPEG, Wavelet) Video conferencingData Sheet, Rev. 0, 11/2008