The ADMV9611 is a complete millimeterwave (mmWave) wireless connectivity solution in a small printed circuit assembly (PCA) format. All millimeterwave signals are confined to the printed circuit assembly, simplifying implementation. Wireless transmission is achieved using the integrated circularly polarized (CP) omnidirectional patch antenna array, which enables communication in many applications, including rotation. Following the antenna array is an integrated diplexer that provides isolation between the separate transmit and receive paths on the board, which reduces multipath distortion. The receive path integrates all components to demodulate the 58.0125 GHz frequency to baseband signals. The flexible receiver gain control is programmable over a wide range to easily accommodate the required link budget. The receiver baseband outputs are dc-coupled and can provide over 500 mV of differential output signal level. Likewise, the transmit path integrates all components to modulate input baseband signals to 63 GHz. The transmitter has programmable gain control to maintain level transmit power. The transmit baseband inputs are dc-coupled and have a broad common-mode input range. Synthesizers are integrated to maintain excellent frequency stability vs. temperature. The simple amplitude modulation (AM) scheme eliminates the need for external data converters, allowing for bit rates of greater than 100 Mbps. On-board power management is integrated to a single 5 V voltage rail to power the ADMV9611.Together with the ADMV9621, the ADMV9611 provides a complete, full duplexed 60 GHz data link for high speed data transmission in the unlicensed 60 GHz industrial, scientific, and medical (ISM) band.APPLICATIONS60 GHz short data link for industrial and medical high data rate applicationsHigh speed data for rotating applications, such as slip rings and magnetic resonance imaging systems

The ADRF5027 is a nonreflective, single-pole, double-throw (SPDT) radio frequency (RF) switch manufactured in a silicon process.The ADRF5027 operates from 9 kHz to 44 GHz with better than 3.8 dB of insertion loss and 43 dB of isolation. The ADRF5027 features an all off control, where both RF ports are in an isolation state. The ADRF5027 has a nonreflective design and both of the RF ports are internally terminated to 50 ?.The ADRF5027 requires a dual-supply voltage of +3.3 V and ?3.3 V. The device employs complimentary metal-oxide semiconductor/low-voltage transistor-transistor logic (CMOS/LVTTL) logic-compatible controls.The ADRF5027 is pin compatible with the ADRF5026 fast switching version, which operates from 100 MHz to 44 GHz.The ADRF5027 RF ports are designed to match a characteristic impedance of 50 ?. For ultrawideband products, impedance matching on the RF transmission lines can further optimize high frequency insertion loss and return loss characteristics. Refer to the Narrow-Band Impedance Matching section for an example of a matched circuit that achieves a low insertion loss response of 2.2 dB from 28 GHz to 43 GHz.The ADRF5027 comes in a 20-terminal, 3 mm ? 3 mm, RoHS-compliant, land grid array (LGA) package and can operate from ?40?C to +105?C.Applications Industrial scanners Test and instrumentation Cellular infrastructure: 5G mmWave Military radios, radars, electronic counter measures (ECMs) Microwave radios and very small aperture terminals (VSATs)

Demonstration circuit 1046A is a non-isolated, high efficiency buck-boost DC/DC supply featuring LTC3780EG and LTC4440ES6. The LTC3780 is a high performance 4-switch synchronous buck boost regulator and the LTC4440 is a 100V-rated FET driver. The input voltage of the demo board is designed for 36V to 72V. The output voltage is 48V. At 25C° room temperature, the maximum output current is 5A without a cooling fan and 6A with 150LFM air flow for cooling. An optional 12V bias flyback supply using the LTC3803 is stuffed on the board to power the LTC3780 and LTC4440.

Demonstration circuit DC1081 is a dual-output low VIN step-down power supply featuring the LTC3836, a low quiescent current, 2-phase synchronous buck controller. The input voltage is from 2.75V to 4.5V. The demo board has two outputs: 1.8V/12A and 1.2V/12A.

The LT3510 is a dual current mode PWM step-down DC/DC converter with two internal 2.5A switches. Independent input voltage, feedback, soft-start and power good pins for each channel simplify complex power supply tracking/sequencing requirements.Both converters are synchronized to either a common external clock input or a resistor programmable ?xed 250kHz to 1.5MHz internal oscillator. At all frequencies, a 180? phase relationship between channels is maintained, reducing voltage ripple and component size. Programmable frequency allows for optimization between efficiency and external component size.Minimum input-to-output voltage ratios are improved by allowing the switch to stay on through multiple clock cycles, only switching off when the boost capacitor needs recharging, resulting in ~95% maximum duty cycle.Each output can be independently disabled using its own soft-start pin, or by using the SHDN pin the entire part can be placed in a low quiescent current shutdown mode.The LT3510 is available in a 20-lead TSSOP package with exposed leadframe for low thermal resistance.Applications DSP Power Supplies Disc Drives DSL/Cable Modems Wall Transformer Regulation Distributed Power Regulation PCI Cards

The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. The PLL section consists of a programmable reference divider (R); a low noise phase frequency detector (PFD); a precision charge pump (CP); and a programmable feedback divider (N). By connecting an external VCXO or VCO to the CLK2/CLK2B pins, frequencies up to 1.6 GHz may be synchronized to the input reference. There are five independent clock outputs. Three outputs are LVPECL (1.2 GHz), and two are selectable as either LVDS (800 MHz) or CMOS (250 MHz) levels.Each output has a programmable divider that may be bypassed or set to divide by any integer up to 32. The phase of one clock output relative to another clock output may be varied by means of a divider phase select function that serves as a coarse timing adjustment. One of the LVDS/CMOS outputs features a programmable delay element with full-scale ranges up to 10 ns of delay. This fine tuning delay block has 5-bit resolution, giving 32 possible delays from which to choose for each full-scale setting. The AD9511 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter. The AD9511 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5.5 V. The temperature range is ?40?C to +85?C. APPLICATIONSLow jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDS, DDC, DUC, MxFEsHigh performance wireless transceiversHigh performance instrumentationBroadband infrastructure

The AD9571 provides a multioutput clock generator function comprising a dedicated PLL core that is optimized for Ethernet line card applications. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.The PLL section consists of a low noise phase frequency detector (PFD), a precision charge pump (CP), a low phase noise voltage controlled oscillator (VCO), and a preprogrammed feedback divider and output divider. By connecting an external crystal or reference clock to the REFCLK pin, frequencies up to 156.25 MHz can be locked to the input reference.Each output divider and feedback divider ratio is preprogrammed for the required output rates. No external loop filter components are required, thus conserving valuable design time and board space.The AD9571 is available in a 40-lead 6 mm ? 6 mm lead frame chip scale package and can be operated from a single 3.3 V supply. The operating temperature range is ?40?C to +85?C.APPLICATIONS Ethernet line cards, switches, and routers SCSI, SATA, and PCI-express PCI support included Low jitter, low phase noise clock generation

The AD9577 provides a multioutput clock generator function,along with two on-chip phase-locked loop cores, PLL1 and PLL2,optimized for network clocking applications. The PLL designsare based on the Analog Devices, Inc., proven portfolio of highperformance, low jitter frequency synthesizers to maximizenetwork performance. The PLLs have I2C programmable outputfrequencies and formats. The fractional-N PLL can supportspread spectrum clocking for reduced EMI radiated peak power.Both PLLs can support frequency margining. Other applicationswith demanding phase noise and jitter requirements can benefitfrom this part.The first integer-N PLL section (PLL1) consists of a low noise phasefrequency detector (PFD), a precision charge pump (CP), a lowphase noise voltage controlled oscillator (VCO), a programmablefeedback divider, and two independently programmable outputdividers. By connecting an external crystal or applying a referenceclock to the REFCLK pin, frequencies of up to 637.5 MHz canbe synchronized to the input reference. Each output divider andfeedback divider ratio is I2C programmed for the requiredoutput rates.A second fractional-N PLL (PLL2) with a programmable modulusallows VCO frequencies that are fractional multiples of thereference frequency to be synthesized. Each output dividerand feedback divider ratio can be programmed for the requiredoutput rates, up to 637.5 MHz. This fractional-N PLL can alsooperate in integer-N mode for the lowest jitter.Up to four differential output clock signals can be configuredas either LVPECL or LVDS signaling formats. Alternatively,the outputs can be configured for up to eight CMOS outputs.Combinations of these formats are supported. No external loopfilter components are required, thus conserving valuable designtime and board space. The AD9577 is available in a 40-lead, 6 mm ?6 mm LFCSP package and can operate from a single 3.3 V supply.The operating temperature range is ?40?C to +85?C.Applications Low jitter, low phase noise multioutput clock generator for data communications applications including Ethernet, Fibre Channel, SONET, SDH, PCI-e, SATA, PTN, OTN, ADC/DAC, and digital video Spread spectrum clocking

The ADAR1000 is a 4-channel, X and Ku frequency band, beamforming core chip for phased arrays. This device operates in half-duplex between receive and transmit modes. In receive mode, input signals pass through four receive channels and are combined and output at the common RF_IO pin. In transmit mode, the RF_IO input signal is split and passes through the four transmit channels. In both modes, the ADAR1000 provides a ?31 dB gain adjustment range and a full 360? phase adjustment range in each radio frequency (RF) channel, with 6-bit resolution (less than ?0.5 dB and 2.8?, respectively).A simple 4-wire serial port interface (SPI) controls all of the on-chip registers. In addition, two address pins allow SPI control of up to four devices on the same serial lines. Dedicated transmit and receive load pins also provide synchronization of all ADAR1000 chips in the same array, and a single pin controls fast switching between the transmit and receive modes. The ADAR1000 is fabricated in a silicon-germanium, bipolar CMOS (BiCMOS) process. The device is available in a compact, 88-terminal, 7 mm ? 7 mm, LGA package and is specified from ?40?C to +85?C.APPLICATIONS Phased array radar Satellite communications systems

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