The AD9520-0 provides a multi-output clock distributionfunction with sub-picosecond jitter performance, along with anon-chip PLL and VCO. The on-chip VCO tunes from 2.53 GHzto 2.95 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHzcan also be used.The AD9520-0 serial interface supports both SPI and I2C ports.An in-package EEPROM, which can be programmed through theserial interface, can store user-defined register settings forpower-up and chip reset.The AD9520-0 features 12 LVPECL outputs in four groups. Anyof the 1.6 GHz LVPECL outputs can be reconfigured as two250 MHz CMOS outputs. If an application requires LVDSdrivers instead of LVPECL drivers, refer to the AD9522-0.Each group of three outputs has a divider that allows both thedivide ratio (from 1 to 32) and the phase offset or coarse timedelay to be set.The AD9520-0 is available in a 64-lead LFCSP and can be operatedfrom a single 3.3 V supply. The external VCO can have anoperating voltage of up to 5.5 V. A separate output driver powersupply can be from 2.375 V to 3.465 V.The AD9520-0 is specified for operation over the standardindustrial range of ?40?C to +85?C. Applications Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation Broadband infrastructures

The AD9522-21 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.02 GHz to 2.335 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used.The AD9522 serial interface supports both SPI and I2C? ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset.The AD9522 features 12 LVDS outputs in four groups. Any of the 800 MHz LVDS outputs can be reconfigured as two 250 MHz CMOS outputs.Each group of outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase (coarse delay) to be set.The AD9522 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage up to 5.5 V.The AD9522 is specified for operation over the standard industrial range of ?40?C to +85?C.The AD9520-2 is an equivalent part to the AD9522-2 featuring LVPECL/CMOS drivers instead of LVDS/CMOS drivers.1The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-2 is used, it is referring to that specific member of the AD9522 family.ApplicationsLow jitter, low phase noise clock distributionClock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocolsForward error correction (G.710)Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEsHigh performance wireless transceiversATE and high performance instrumentationBroadband infrastructures

The 10 clock outputs of the AD9542 are synchronized to any one of up to four input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail.The AD9542 is available in a 48-lead LFCSP (7 mm ? 7 mm) package and operates over the ?40?C to +85?C temperature range.Note that throughout this data sheet, multifunction pins, such as SDO/M5, are referred to either by the entire pin name or by a single function of the pin, for example, M5, when only that function is relevant.Applications SyncE jitter cleanup and synchronization Optical transport networks (OTN), SDH, and macro and small cell base stations OTN mapping/demapping with jitter cleaning Small base station clocking, including baseband and radio Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking Cable infrastructures Carrier Ethernet

The AD9543 supports existing and emerging ITU standards for the delivery of frequency, phase, and time of day over service provider packet networks.The 10 clock outputs of the AD9543 are synchronized to any one of up to four input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail.The AD9543 is available in a 48-lead LFCSP (7 mm ? 7 mm) package and operates over the ?40?C to +85?C temperature range.Note that throughout this data sheet, multifunction pins, such as SDO/M5, are referred to either by the entire pin name or by a single function of the pin, for example, M5, when only that function is relevant.Appliations PTP (IEEE 1588), and SyncE jitter cleanup and synchronization Optical transport networks (OTN), SDH, and macro and small cell base stations OTN mapping/demapping with jitter cleaning Small base station clocking, including baseband and radio Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking Cable infrastructures Carrier Ethernet

The AD9552 is a fractional-N phase locked loop (PLL) based clock generator designed specifically to replace high frequency crystal oscillators and resonators. The device employs a sigma-delta (?-?) modulator (SDM) to accommodate fractional frequency synthesis. The user supplies an input reference signal by connecting a single-ended clock signal directly to the REF pin or by connecting a crystal resonator across the XTAL pins.The AD9552 is pin programmable, providing one of 64 standard output frequencies based on one of eight common input frequencies. The device also has a 3-wire SPI interface, enabling the user to program custom input-to-output frequency ratios.The AD9552 relies on an external capacitor to complete the loop filter of the PLL. The output is compatible with LVPECL, LVDS, or single-ended CMOS logic levels, although the AD9552 is implemented in a strictly CMOS process.The AD9552 is specified to operate over the extended industrial temperature range of ?40?C to +85?C.APPLICATIONS Cost effective replacement of high frequency VCXO, OCXO, and SAW resonators Extremely flexible frequency translation with low jitter for SONET/SDH (including FEC) , 10 Gb Ethernet, Fibre Channel, and DRFI/DOCSIS High-definition video frequency translation Wireless infrastructure Test and measurement (including handheld devices)

The AD9553 is a phase-locked loop (PLL) based clock translator designed to address the needs of passive optical networks (PON) and base stations. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. The user supplies up to two single-ended input reference signals or one differential input reference signal via the REFA and REFB inputs. The device supports holdover applications by allowing the user to connect a 25 MHz crystal resonator to the XTAL input.The AD9553 is pin programmable, providing a matrix of standard input/output frequency translations from a list of 15 possible input frequencies to a list of 52 possible output frequency pairs (OUT1 and OUT2). The device also has a 3-wire SPI interface, enabling the user to program custom input-to-output frequency translations.The AD9553 output is compatible with LVPECL, LVDS, or single-ended CMOS logic levels, although the AD9553 is implemented in a strictly CMOS process.The AD9553 operates over the extended industrial temperature range of ?40?C to +85?C.APPLICATIONS Cost effective replacement of high frequency VCXO, OCXO, and SAW resonators Extremely flexible frequency translation for SONET/SDH, Ethernet, Fibre Channel, DRFI/DOCSIS, and PON/EPON/GPON Wireless infrastructure Test and measurement (including handheld devices)

The AD9911 is a complete direct digital synthesizer (DDS).This device includes a high speed DAC with excellent widebandand narrowband spurious-free dynamic range (SFDR) as well asthree auxiliary DDS cores without assigned digital-to-analogconverters (DACs). These auxiliary channels are used for spurreduction, multitone generation, or test-tone modulation.The AD9911 is the first DDS to incorporate SpurKillertechnology and multitone generation capability. Multitonemode enables the generation up to four concurrent carriers;frequency, phase and amplitude can be independentlyprogrammed. Multitone generation can be used for systemtests, such as inter-modulation distortion and receiver blockersensitivity. SpurKilling enables customers to improve SFDRperformance by reducing the magnitude of harmoniccomponents and/or the aliases of those harmonic components.Test-tone modulation efficiently enables sine wave modulationof amplitude on the output signal using one of the auxiliaryDDS cores.The AD9911 can perform modulation of frequency, phase, oramplitude (FSK, PSK, ASK). Modulation is implemented bystoring profiles in the register bank and applying data to theprofile pins. In addition, the AD9911 supports linear sweep offrequency, phase, or amplitude for applications such as radarand instrumentation.The DDS acts as a high resolution frequency divider with theREF_CLK as the input and the DAC providing the output. TheREF_CLK input can be driven directly or used in combinationwith an integrated REF_CLK multiplier (PLL). The REF_CLKinput also features an oscillator circuit to support an externalcrystal as the REF_CLK source. The crystal can be used incombination with the REF_CLK multiplier.The AD9911 I/O port offers multiple configurations to providesignificant flexibility. The I/O port offers an SPI-compatiblemode of operation that is virtually identical to the SPI operationfound in earlier Analog Devices DDS products.Flexibility is provided by four data pins (Pin SDIO_0,Pin SDIO_1, Pin SDIO_2, and Pin SDIO_3) that allow fourprogrammable modes of I/O operation.The DAC output is supply referenced and must be terminatedinto AVDD by a resistor and an AVDD center-tapped transformer.The DAC has its own programmable reference to enabledifferent full-scale currents.The DDS core (the AVDD pins and the DVDD pins) is poweredby a 1.8 V supply. The digital I/O interface (SPI) operates at3.3 V and requires that the Pin DVDD_I/O (Pin 49) beconnected to 3.3 V. Applications Agile local oscillator Test and measurement equipment Commercial and amateur radio exciter Radar and sonar Test-tone generation Fast frequency hopping Clock generation

The AD9956 is Analog Devices?s first AgileRF synthesizer.The device is comprised of a DDS and PLL circuitry. The DDSfeatures a 14-bit DAC operating up to 400 MSPS and a 48-bitfrequency tuning word. The PLL Circuitry includes a phasedetector with scaleable 200 MHz inputs (pre-scalar inputsoperate up to 650 MHz) and digital control over the chargepump current. The device also includes a 650 MHz PECL driverwith programmable slew rates.The AD9956 uses advanced DDStechnology, an internal high-speed, high performance D/Aconverter and an advance phase-detector/charge pumpcombination to enable the synthesis of digitally-programmable,frequency-agile analog output sinusoidal waveforms up to2.7 GHz. The AD9956 is designed to provide fast frequencyhopping and fine tuning resolution (48-bit frequency tuningword). Information is loaded into the AD9956 via a serial I/Oport which has a device write speed of 25 MBit/sec. The AD9956DDS block also supports a user defined linear sweep mode ofoperation.The AD9956 is specified to operate over the extendedautomotive range of ?40?C to +125?C.Applications Agile LO frequency synthesis FM chirp source for radar and scanning systems Automotive radars Test and measurement equipment Acousto-optic device drivers

The AD9957 functions as a universal I/Q modulator and agileupconverter for communications systems where cost, size, powerconsumption, and dynamic performance are critical. TheAD9957 integrates a high speed, direct digital synthesizer(DDS), a high performance, high speed, 14-bit digital-to-analogconverter (DAC), clock multiplier circuitry, digital filters, andother DSP functions onto a single chip. It provides basebandupconversion for data transmission in a wired or wirelesscommunications system.The AD9957 is the third offering in a family of quadraturedigital upconverters (QDUCs) that includes the AD9857 andAD9856. It offers performance gains in operating speed, powerconsumption, and spectral performance. Unlike its predecessors,it supports a 16-bit serial input mode for I/Q baseband data.The device can alternatively be programmed to operate either asa single tone, sinusoidal source or as an interpolating DAC.The reference clock input circuitry includes a crystal oscillator,a high speed, divide-by-two input, and a low noise PLL formultiplication of the reference clock frequency.The user interface to the control functions includes a serial porteasily configured to interface to the SPORT of the Blackfin?DSP and profile pins to enable fast and easy shift keying of anysignal parameter (phase, frequency, or amplitude).Applications HFC data, telephony, and video modems Wireless base station transmissions Broadband communications transmissions Internet telephony

The ADCLK846 is a 1.2 GHz/250 MHz, LVDS/CMOS, fanout buffer optimized for low jitter and low power operation. Possible configurations range from 6 LVDS to 12 CMOS outputs, including combinations of LVDS and CMOS outputs. Two control lines are used to determine whether fixed blocks of outputs are LVDS or CMOS outputs.The clock input accepts various types of single-ended and differential logic levels including LVPECL, LVDS, HSTL, CML, and CMOS.Table 8 provides interface options for each type of connection. The SLEEP pin enables a sleep mode to power down the device.This device is available in a 24-pin LFCSP package. It is specified for operation over the standard industrial temperature range of ?40?C to +85?C.APPLICATIONS Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation