Power Management IC Development Tools 2.75V to 6V, 1A, Ultra-Small, Ultra-Low Noise Power Module Evaluation Board

EVAL BOARD WIRELESS TX BQ500414Q

The LTC4162-S is an advanced monolithic synchronous step-down switching battery charger and PowerPath? manager that seamlessly manages power distribution between input sources such as wall adapters, backplanes, solar panels, etc., and a lead-acid battery.A high resolution measurement system provides extensive telemetry information for circuit voltages, currents, battery resistance and temperature which can all be read back over the I2C port. The I2C port can also be used to configure many charging parameters including charging voltages and currents, termination algorithms and numerous system status alerts.The LTC4162-S can charge 6V, 12V, 18V and 24V lead-acid batteries with as much as 3.2A of charge current.The power path topology decouples the output voltage from the battery allowing a portable product to start up instantly under very low battery voltage conditions.The LTC4162-S is available in a thermally enhanced 28-pin 4mm ? 5mm ? 0.75mm QFN surface mount package.Applications Medical Instruments USB-C Power Delivery Industrial Handhelds Ruggedized Notebook Tablet Computers

The AD9650 is a dual, 16-bit, 25 MSPS/65 MSPS/80 MSPS/ 105 MSPS analog-to-digital converter (ADC) designed for digitizing high frequency, wide dynamic range signals with input frequencies of up to 300 MHz.The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers, and shared integrated voltage reference, which eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.The ADC output data can be routed directly to the two external 16-bit output ports or multiplexed on a single 16-bit bus. These outputs can be set to either 1.8 V CMOS or LVDS.Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.The AD9650 is available in a 64-lead LFCSP and is specified over the industrial temperature range of ?40?C to +85?C.PRODUCT HIGHLIGHTS On-chip dither option for improved SFDR performance with low power analog input. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 300 MHz. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, and test modes. Pin compatible with the AD9268 and other dual families, AD9269, AD9251, AD9231, and AD9204. This allows a simple migration across resolutions and bandwidth.?APPLICATIONS Industrial instrumentation X-Ray, MRI, and ultrasound equipment High speed pulse acquisition Chemical and spectrum analysis Direct conversion receivers Multimode digital receivers Smart antenna systems General-purpose software radios

ADS1220 evaluation module

Demonstration circuit 3051A features the LTM4705, a high efficiency dual 5A or single 10A μModule® DC/DC regulator in a compact and low profile 6.25mm × 7.5mm × 3.22mm BGA package. The LTM4705 can take 3.1V to 20V input and generate 0.6V to 5.5V output (stepdown only). The DC3051A demo board is designed to take 6VIN to 20VIN to dual 5A jumper selectable outputs. The board operates by default at a fixed 1MHz and can be synchronized from 1MHz to 3MHz via the MODE/SYNC pin. With its high switching frequency and current mode architecture, a fast transient response to line and load changes is possible without sacrificing stability. The DC3051A can be used in forced continuous mode or pulse-skipping mode for low noise, or in Burst Mode® operation for high efficiency at light loads. Please see the LTM4705 data sheet for more detailed information. It is recommended to read the data sheet for the LTM4705 prior to making any changes to the DC3051A.

TPS61085 Evaluation Module

Demonstration circuit DC1997A is a dual output synchronous buck converters featuring the LTC3838EUHF-1 (DC1997A-A) or the  LTC3838EUHF-2 (DC1997A-B). Both assemblies provide two outputs of 1.5V/20A and 1.2V/20A over an input voltage range of 4.5V to 14V at a switching frequency of 300kHz. The LTC3838-1 and LTC3838-2 provide dual differential VOUT sensing while the dual LTC3838 (plain) has differential VOUT sensing on one channel. The "-2" version has an external reference input for channel 2.

The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40?C to +85?C industrial temperature range. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm ? 9 mm, 64-lead LFCSP.APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

DAC8568 Low-power; Voltage-output; 8-channel; 16-bit DAC BoosterPack