The HMC1133LP5E is a 6-bit digital phase shifter which is rated from 4.0 to 7 GHz, providing 360 degrees of phase coverage, with a LSB of 5.625 degrees. The HMC1133LP5E features very low RMS phase error of 2.8 degrees and extremely low insertion loss variation of ?0.4 dB across all phase states. This high accuracy phase shifter is controlled with positive control logic of 0/+5V The HMC1133LP5E is housed in a compact 5x5 mm plastic leadless SMT package and is internally matched to 50 Ohms with no external components.Applications EW Receivers Weather & Military Radar Satellite Communications Beamforming Modules Phase Cancellation

The HMC1161 is a monolithic microwave integrated circuit (MMIC), voltage controlled oscillator (VCO) that integrates a resonator, a negative resistance device, and a varactor diode, and features a half frequency output. Because of the monolithic construction of the oscillator, the output power and phase noise performance are excellent over temperature.The output power is 11 dBm typical from a 5 V supply voltage. The VCO is housed in a RoHS-compliant LFCSP and requires no external matching components.Applications Point to point and multipoint radios? Test equipment and industrial controls? Very small aperture terminals (VSATs)?

The HMC199AMS8 & HMC199AMS8E are low-cost general purpose dual SPDT GaAs ?bypass? switches in 8-lead MSOP packages covering DC to 2.5 GHz. These four-RF-port components integrate two SPDT switches and a through line onto a single IC. The designs provide low insertion loss of less than 0.5 dB while switching passive or active external circuit components in and out of the signal path. Port to port isolations are typically 25 to 30 dB. On-chip circuitry enables positive voltage control operation at very low DC currents with control inputs compatible with CMOS and most TTL logic families. Applications include LNA or filter bypass switching and single bit attenuator switching. The HMC199AMS8E is a RoHS-compliant product.APPLICATIONS Cellular ISM Basestations PCS

The HMC244AG16 is a non-reflective SP4T switch ina 16 lead glass/metal (hermetic) package. CoveringDC to 4 GHz, the switch offers 30~50 dB isolationand a low insertion loss of 0.9 dB through 3 GHz. A2:4 TTL/CMOS compatible decoder is integrated onthe switch requiring only 2 control lines and a positive5V bias to select each path, replacing 8 control linesnormally required by GaAs SP4T switches.Applications Telecom infrastructure Military radios, radar and ECM Space applications Test instrumentation

The HMC252AQS24E is low-cost non-reflectiveSP6T switches in 24-lead QSOP packagesfeaturing wideband operation from DC to3.0 GHz. The switch offers a single positive biasand true TTL/CMOS compatibility. A 3:6 decoderis integrated on the switch requiring only 3 controllines and a positive bias to select each path.The HMC252AQS24E SP6T replaces multipleconfigurations of SP4T and SPDT MMIC switches andlogic drivers.Applications Base station CATV / DBS MMDS and wireless LAN Test equipment

The HMC260ALC3B is a general-purpose, double balanced,monolithic microwave integrated circuit (MMIC) mixer housed in a leadless, Pb-free, RoHS compliant LCC package. The devicecan be used as an upconverter or downconverter in the 10 GHz to 26 GHz frequency range. The HMC260ALC3B mixer requires no external components or matching circuitry.The HMC260ALC3B provides local oscillator (LO) to radiofrequency (RF) and LO to intermediate frequency (IF) suppression due to optimized balun structures. The mixer operates with LO amplitude levels between 9 dBm and 15 dBm.The HMC260ALC3B eliminates the need for wire bonding,allowing the use of surface-mount manufacturing techniques.Applications Point to point radios Point to multipoint radios and very small aperture terminals (VSATs) Test equipment and sensors Military end use

The HMC305SLP4E is a broadband 5-bit positivecontrol Silicon IC digital attenuator with CMOS compatibleserial-to-parallel driver package in a leadlessQFN 4x4 mm SMT package. Covering 0.4 to 6GHz, the insertion loss is typically less than 1.6 dB.The attenuator bit values are 0.5 (LSB), 1, 2, 4, and8 dB for a total attenuation of 15.5 dB. Attenuationaccuracy is excellent at ?0.25 dB typical with an IIP3of up to +52 dBm. Five bit serial control words areused to select each attenuation state. A single Vccbias of +3.3V to +5V is required.The HMC305S(E) is a replacement for the HMC305A(E), HMC305B(E) and HMC305(E).Applications Cellular Infrastructure Wireless Infrastructure Microwave Radio & VSAT Test Instrumentation

The ADMV4540 is a highly integrated quadrature demodulator with integrated synthesizer ideally suited for next generation K band satellite communication.The RF front end of the ADMV4540 consists of two low noise amplifier (LNA) paths, each with an optimal cascaded, 5 dB, double sideband noise figure at maximum gain, while minimizing external components. The dual paths allow support for antenna polarization. Selection of the LNA path can be done through the SPI.The LNA output is then downconverted to baseband using an inphase and quadrature (I/Q) mixer. The I/Q mixer output is then fed into fully differential low noise and low distortion programmable filters and variable gain amplifiers (VGAs). Each channel is capable of rejecting large, out of band interferers while reliably boosting the wanted signal, thus reducing the bandwidth and resolution requirements on the analog-to-digital converters (ADCs) of the system. The excellent matching between channels and their highspurious-free dynamic range (SFDR) over all gain and bandwidth settings make the ADMV4540 ideal for satellite communication systems with dense constellations, multiple carriers, and nearby interferers.The three filter corners of 125 MHz, 250 MHz, and 500 MHz are all programmable via a serial peripheral interface (SPI). The filters provide a sixth-order Butterworth response with ?3 dB corner frequencies of 141 MHz, 282 MHz, and 565 MHz. For operation beyond 565 MHz, the filter can be disabled and completely bypassed, thereby extending the ?3 dB bandwidth up to 900 MHz.The high dynamic range baseband output amplifiers of the ADMV4540 provide an overall nominal conversion gain of 57 dB. The three baseband voltage variable attenuator (VVA) pins (VCTRL_BBVVAx) of the ADMV4540 can be used for automatic gain control (AGC), giving the ADMV4540 a wide RF input dynamic range.This feature rich device contains an integrated fractional-N phase-locked loop (PLL) and a low phase noise voltage controlled oscillator (VCO) that generates the necessary on-chip local oscillator (LO) signal for the two double balanced I/Q mixers, eliminating the need for external frequency synthesis. The VCO utilizes an internal automatic calibration routine that allows the PLL to select the necessary settings and lock.The reference input (REFIN) to the PLL of the ADMV4540 employs a differentially excited crystal oscillator at 50 MHz. Alternatively, the REFIN can be driven by an external single-ended frequency reference up to 100 MHz. The phase frequency detector (PFD) comparison frequency operates up to 100 MHz, which allows for continuous LO coverage from 17 GHz to 21.5 GHz in extremely fine steps.The ADMV4540 operates on a 3.3 V supply with less than 3.2 W of total power dissipation. It is available in a 48-terminal, RoHS compliant, 7 mm ? 7 mm LGA package with an exposed paddle. The ADMV4540 can operate over the ?40? to +85? temperature range on a + 3.3 V power supply.APPLICATIONSSatellite communications

The ADMV4801 is a silicon germanium (SiGe), 24 GHz to 29.5 GHz, mmW, 5G beamformer. This RF IC is highly integrated and contains 16 independent transmit and receive channels. In transmit mode, the RFC input signal is split using 1:16 power splitters and passes through the 16 independent transmit channels. In receive mode, input signals pass through the 16 independent channels and are combined with 16:1 combiners to the RFC pin. In transmit mode, each channel includes a vector modulator (VM) to control phase and two digital variable gain amplifiers (DVGAs) to control amplitude. In receive mode, each channel includes a VM to control phase and a DVGA to control amplitude. The VM provides a full 360? phase adjustment range in either transmit or receive mode, providing 6 bits of resolution for 5.625? phase steps. The total DVGA dynamic range adjustment range in transmit mode is 34 dB, providing 6 bits of resolution, resulting in 0.5 dB amplitude steps, and 5 bits of resolution, resulting in 1 dB amplitude steps. In receive model the total dynamic range is 17 dB providing, 6 bits of resolution, resulting in 0.5 dB amplitude steps. The DVGAs provide a flat phase response across the full gain range. The transmit channels contain individual power detectors to provide the ability to detect and calibrate each channel gain, as well as channel to channel gain mismatch. The ADMV4801 RF ports can be connected directly to a patch antenna to create a dual polarization, mmW, 5G subarray.The programming of the ADMV4801 can be accomplished using the 3-wire or 4-wire serial port interface (SPI). An integrated, onchip low dropout regulator (LDO) generates the 1.8 V supply for the SPI circuitry to reduce the number of required supply domains. Various SPI modes are available to enable fast startup and control during normal operation. The amplitude and phase for each channel can be set individually, or multiple channels can be programmed simultaneously using the on-chip memory for beamforming. The on-chip memory can store up to 256 beam positions, which can be allocated for either transmit or receive mode. A dedicated load pin provides synchronization of all devices in the same array. A transmit and receive mode control pin is provided for fast switching between transmit and receive mode.The ADMV4801 is featured in a compact, thermally enhanced, 10 mm ? 10 mm, RoHS compliant land grid array (LGA) package. The ADMV4801 operates over the ?40?C to +95?C case temperature range. This LGA package enables the ability to heat-sink the ADMV4801 from the topside of the package for the most efficient thermal heat-sinking and to allow flexible antenna placement on the opposite side of the printed circuit board (PCB).Throughout the figures in the data sheet, Tx means transmit (or transmitter) and Rx means receive (or receiver).Additional digital details of ADMV4801 are available in AN-2021 Application Note, ADMV4801 SPI Application Note. Contact Analog Devices at mmWave5G@analog.com.APPLICATIONS5G applicationsBroadband communicationTest and measurementAerospace and defense

The ADMV4828 is a silicon on insulator (SOI), 24.0 GHz to 29.5 GHz, mmW 5G beamformer. The RF integrated circuit (RFIC) is highly integrated and contains 16 independent transmit and receive channels. The ADMV4828 supports eight horizontal and eight vertical polarized antennas via independent RFV and RFH input/outputs.In transmit mode, both the RFV input and RFH input signals feed into separate amplifiers. Each path after the amplifiers splits into eight independent channels via the 1:8 power splitters. In receive mode, input signals pass through either the vertical or horizontal receive channels and combine via two independent 8:1 combiners to the common RFV pin or RFH pin. In either mode, each transmit and receive channel includes a vector modulator (VM) to control the phase, and two digital variable gain amplifiers (DVGAs) to control the amplitude. The VM provides a full 360? phase adjustment range in either transmit or receive mode to provide 6 bits of resolution for 5.625? phase steps. A phase step policy for the transmit and receive VM is provided to ensure optimum phase step performance. The total DVGA dynamic range in transmit mode is 34.5, which provides 6 bits of resolution that results in 0.5 dB amplitude steps and 5 bits of resolution that results in 1 dB amplitude steps. In receive mode, the total dynamic range is 28 dB, which provides 5 bits of resolution that results in 0.5 dB amplitude steps and 5 bits of resolution that results in 1 dB amplitude steps. The DVGAs provide a flat phase response across the full gain range. A gain policy for DVGA1 and DVGA2 is provided in the AN-2074 Application Note, ADMV4828 Application Note to ensure optimized performance across the attenuation range with 0.5 dB step resolution from 0 dB to 34.5 dB attenuation for transmit mode and 0.5 dB step resolution from 0 dB to 28 dB attenuation for receive mode. The transmit channels contain individual transmit power detectors to detect either modulated or continuous wave signals to calibrate for each channel gain as well as channel to channel gain mismatch. Each receive channel contains an RF power overload circuit (receive channel overload detection circuit) to prevent potential damage to the device as a result of blocker instances. The ADMV4828 RF ports can be connected directly to a patch antenna to create a dual polarization mmW 5G subarray.The ADMV4828 can be programmed using a 3-wire or 4-wire serial port interface (SPI). An integrated, on-chip low dropout (LDO) voltage regulator generates the 1.0 V supply for the SPI circuitry to reduce the number of supply domains required. Various SPI modes are available to enable fast startup and control during normal operation. The amplitude and phase for each channel can be set individually or multiple channels can be programmed simultaneously using the on-chip memory for beamforming. The on-chip memory can store up to 2048 beam positions that can be allocated for either transmit mode or receive mode for the horizontal channels and vertical channels. On-chip nonvolatile memory (NVM) is used to store the calibrated gain and phase offset coefficients and the reference values for each individual channel from the factory. These values are used to perform channel to channel or chip to chip calibration. In addition, four address pins (CHIP_ADDx) allow independent SPI control of up to 16 devices on the same serial lines. To control multiple devices via the same serial lines with the same instructions, activate broadcast mode via the external enable pin (BR_EN). Dedicated horizontal and vertical polarization load pins (LOAD_V and LOAD_H) provide the synchronization of all devices in the same array. A horizontal and vertical polarization transmit mode and receive mode control pin (TRX_H or TRX_V) is provided for fast switching between transmit mode and receive mode.The ADMV4828 comes in a compact, 304-ball, 10 mm ? 8.5 mm chip scale package ball grid array (CSP_BGA). The ADMV4828 operates over the ?40?C to +95?C case temperature (TC) range. This CSP_BGA package enables the ability to heatsink the ADMV4828 from the topside of the package for the most efficient thermal heatsinking and to allow flexible antenna placement on the opposite side of the printed circuit board (PCB).APPLICATIONSmmW 5G applicationBroadband communication