Demonstration circuit 2624A features the LT3094, an ultralow noise, ultrahigh power supply rejection ratio (PSRR) negative low dropout (LDO) regulator. DC2624A operates over an input range of –3.8V to –20V, and can deliver up to 500mA output current. It features ultralow noise (0.8µVRMS from 10Hz to 100kHz) and very high PSRR (75dB at 1MHz). The LT3094 enable function (EN/UVLO pin) is bidirectional and can be controlled with either a positive or a negative voltage. The LT3094 also offers programmable current limit functionality by connecting a resistor from ILIM to GND. Current monitoring is also achieved by sensing the ILIM pin voltage. The VIOC tracking function controls an upstream switching converter to maintain a constant voltage across the regulator and, hence, minimize power dissipation. The power good feedback (PGFB) pin is used to set a programmable power good threshold, and activates the fast start-up circuitry. To use the power good function, connect an external voltage source at VEXT. If power good and fast start-up functionality are not needed, tie PGFB to IN. Built-in protection includes reverse battery protection, reverse current protection, internal current limit with foldback, and thermal limit with hysteresis. The LT3094 data sheet gives a complete description of the part, operation and applications information. The data sheet must be read in conjunction with this demo manual for demonstration circuit DC2624A. The LT3094 is assembled in 12-lead MSOP and 3mm × 3mm DFN packages with an exposed pad on the bottom-side of the IC. Proper board layout is essential for maximum thermal performance.

LMH6583 Customer Evaluation Board (16x16)

The AD9514 features a multi-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.There are three independent clock outputs. Two of the outputs are LVPECL, and the third output can be set to either LVDS or CMOS levels. The LVPECL outputs operate to 1.6 GHz, and the third output operates to 800 MHz in LVDS mode and to 250 MHz in CMOS mode. Each output has a programmable divider, which can be set to divide by a selected set of integers ranging from 1 to 32. The phase of one clock output relative to another clock output can be set by means of a divider phase select function that serves as a coarse timing adjustment. The LVDS/CMOS output features a delay element with three selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each with 16 steps of fine adjustment. The AD9514 does not require an external controller for operation or setup. The device is programmed by means of 11 pins (S0 to S10) using 4-level logic. The programming pins are internally biased to ? VS. The VREF pin provides a level of ? VS. VS (3.3 V) and GND (0 V) provide the other two logic levels. The AD9514 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter. The AD9514 is available in a 32-lead LFCSP and operates from a single 3.3 V supply. The temperature range is ?40?C to +85?C. APPLICATIONSLow jitter, low phase noise clock distribution Clocking high speed ADC, DAC, DDS, DDC, DUC, MxFEsHigh performance wireless transceiversHigh performance instrumentationBroadband infrastructureATE

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