600 mA, Ultralow Noise, High PSRR, RF Linear Regulator Features: Input voltage range: 2.3 V to 5.5 V Output voltage range: 1.2 V to 3.4 V Maximum load current: 600 mA Low noise 0.9 μV rms total integrated noise from 100 Hz to 100 kHz 1.6 μV rms total integrated noise from 10 Hz to 100 kHz Noise spectral density: 1.5 nV/√Hz from 10 kHz to 1 MHz PSRR: >90 dB from 200 Hz to 200 kHz; 57 dB at 1 MHz Dropout voltage: 120 mV typical at VOUT = 3.3 V, IOUT = 600 mA Initial accuracy: ±0.5% Accuracy over line, load, and temperature: −2.0% (minimum), +1.5% (maximum) Quiescent current, IGND = 4 mA at no load Low shutdown current: 0.2 μA Stable with a 10 μF ceramic output capacitor 8-lead LFCSP and 8-lead SOIC packages Precision enable Supported by ADIsimPower tool

5V, 12-Bit, Serial 220 kSPS ADC in a 8-Lead Package Features: Fast 12-Bit ADC with 220 kSPS Throughput Rate 8-Lead SOIC Single 5 V Supply Operation High Speed, Flexible, Serial Interface that Allows Interfacing to 3 V Processors On-Chip Track/Hold Amplifier Selection of Input Ranges: ±10 V for AD7898-10 ±2.5 V for AD7898-3 High Input Impedance Low Power: 22.5 mW Max

5 V Single Supply 14-Bit 400 kSPS ADC Features: Fast (2.2 µs) 14-Bit ADC 400 kSPS Throughput Rate 0.3 µs Track/Hold Acquisition Time Single Supply Operation High-Speed Parallel Interface which Also Allows Interfacing to 3 V Processors Low Power, 80 mW Typ Selection of Input Ranges: ±10 V, ±5 V and ±2.5 V 0 V to 2.5 V and 0 V to 5 V Power-Saving Mode, 20 µW Typ Overvoltage Protection on Analog Inputs Power-Down Mode via STBY Pin

8-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 20-Lead TSSOP Features: Fast throughput rate: 1 MSPS Specified for AVDD of 2.7 V to 5.25 V Low Power: 6.0 mW max at 1 MSPS with 3 V supply 13.5 mW max at 1 MSPS with 5 V supply Eight (single-ended) inputs with sequencer Wide input bandwidth: AD7928, 70 dB min SINAD at 50 kHz input frequency Flexible power/serial clock speed management No pipeline delays High speed serial interface SPI®/QSPI™/MICROWIRE™/DSP compatible

Clock Drivers & Distribution 800MHz Clock Distribution IC pb free

10-Bit, 100 MSPS+ TxDAC D/A Converter Features: Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 10-Bit Resolution Excellent Spurious Free Dynamic Range Performance SFDR to Nyquist @ 40 MHz Output: 52 dBc Differential Current Outputs: 2 ma to 20 mA Edge-Triggered Latches See datasheet for additional features

16-Bit 160 MSPS 2x/4x/8x Interpolating Dual TxDAC+ D/A Converter Features: 16-bit resolution, 160 MSPS/400 MSPS input/output data rate Selectable 2×/4×/8× interpolating filter Programmable channel gain and offset adjustment fS/4, fS/8 digital quadrature modulation capability Fully compatible SPI® port Direct IF transmission mode for 70 MHz + IFs Enables image rejection architecture See datasheet for additional features

Dual, 12-Bit, 1 GSPS, Digital-to-Analog Converter Features: Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS, full operating conditions Single carrier W-CDMA ACLR = 80 dBc @ 80 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Novel 2×, 4×, and 8× interpolator/coarse complex modulator allows carrier placement anywhere in DAC bandwidth Auxiliary DACs allow control of external VGA and offset control Multiple chip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter 100-lead, exposed paddle TQFP

10-/12-Bit Mixed Signal Front-End (MxFE) Processor for Broadband Communications Features: Dual 10-/12-Bit, 64 MSPS Sampling A/D Converter with Independent Reference, Input Buffers, Programmable Gain Amplifiers (PGA), Decimation Filters and a Digital Hilbert Block Dual 12-/14-bit, 128 MSPS D/A Converter with Digital Hilbert and Interpolation Filters, Digital I/Q or Real-Signal Up-Converters, By passable Digital Up-Converters A Versatile Mixed Signal Front-End Processor with Dual Receive and Dual Transmit Channels Internal Clock Distribution Block including a Phase-Locked Loop and Timing Generation circuitry Programmable Output Clocks, SPI Port, Programmable Sigma Delta Outputs, Auxiliary DAC outputs, Auxiliary ADC inputs

Broadband Modem Mixed-Signal Front End Features: Low cost, 3.3 V CMOS MxFE® for broadband modems 10-bit digital-to-analog converter (DAC) 2×/4× interpolation filter 250 MSPS DAC update rate 10-bit, 75 MSPS ADC Low noise RxPGA Dual channel muxed input 6 dB input overload attenuator −12 dB to +48 dB (without attenuator) Third-order programmable low-pass filter Flexible digital datapath interface Half-duplex and full-duplex operation Programmable delay Tx driver disable signal Various power-down/reduction modes Internal clock multiplier (PLL) 2 auxiliary programmable clock outputs 64-lead LFCSP