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CDC421A106RGET
|
| Price |
|
|
|
$0.24 |
|
|
|
|
|
|
$10.52 |
| RoHS |
|
Compliant |
Yes |
Yes |
Yes |
Compliant |
Compliant |
|
Yes |
Compliant |
Yes |
| Lead Status |
|
No |
Yes |
Yes |
Yes |
No |
|
|
Yes |
No |
Yes |
| Operating Frequency Range(Max)(MHz) |
|
|
533 |
|
|
|
|
|
|
|
|
| Operating Frequency Range(Min)(MHz) |
|
|
533 |
|
|
|
|
|
|
|
|
| Package Size |
|
|
mm2 |
mm2 |
mm2 |
mm2 |
|
|
|
|
mm2 |
| Operating Temperature Range(C) |
|
|
-40 to 85 |
-40 to 125 |
-40 to 125 |
-55 to 125 |
|
|
-40 to 105 |
|
-40 to 85 |
| Absolute Jitter (Peak-to-Peak Cycle or Period Jitter)(ps) |
|
|
40 |
|
|
|
|
|
|
|
|
| Rating |
|
|
Catalog |
Catalog |
Catalog |
HiRel Enhanced Product |
|
|
Catalog |
|
|
| Package Group |
|
|
SSOP |
DSBGA,SM8,VSSOP |
SO,SOIC,SSOP,TSSOP,VQFN |
SC70 |
|
|
MSOP-PowerPAD,PDIP,SOIC |
|
VQFN |
| Number of Outputs |
|
|
1 |
|
|
|
|
|
|
|
|
| VCC(V) |
|
|
3.3 |
|
|
|
|
|
|
|
|
| t(phase error)(ps) |
|
|
100 |
|
|
|
|
|
|
|
|
| Output Drive(mA) |
|
|
16 |
|
|
|
|
|
|
|
|
| Approx. Price (US$) |
|
|
2.72 | 1ku |
0.14 | 1ku |
0.08 | 1ku |
|
|
|
1.10 | 1ku |
|
7.00 | 1ku |
| tsk(o)(ps) |
|
|
0 |
|
|
|
|
|
|
|
|
| Function |
|
|
RAMBUS/XDR |
|
|
|
|
|
|
|
|
| 3-State Output |
|
|
|
Yes |
|
No |
|
|
|
|
|
| Voltage(Nom)(V) |
|
|
|
1.8,2.5,3.3,5 |
1.8,2.5,2.7,3.3 |
1.8,2.5,3.3,5 |
|
|
|
|
|
| Technology Family |
|
|
|
LVC |
LVC |
LVC |
|
|
|
|
|
| Output Drive (IOL/IOH)(Max)(mA) |
|
|
|
32/-32 |
24/-24 |
32/-32 |
|
|
|
|
|
| Logic |
|
|
|
True |
|
True |
|
|
|
|
|
| Schmitt Trigger |
|
|
|
No |
No |
No |
|
|
|
|
|
| Gate Type |
|
|
|
BUFFER |
|
|
|
|
|
|
|
| ICC @ Nom Voltage(Max)(mA) |
|
|
|
0.01 |
0.04 |
0.01 |
|
|
|
|
|
| F @ Nom Voltage(Max)(Mhz) |
|
|
|
150 |
70 |
150 |
|
|
|
|
|
| tpd @ Nom Voltage(Max)(ns) |
|
|
|
9.1,4.8,4.3,3.7 |
8.9,7.4,5.4,4.4 |
16,9,8,5 |
|
|
|
|
|
| VCC(Max)(V) |
|
|
|
5.5 |
3.6 |
5.5 |
|
|
|
|
|
| VCC(Min)(V) |
|
|
|
1.65 |
1.5 |
1.65 |
|
|
|
|
|
| Sub-Family |
|
|
|
Non-Inverting Buffer/Driver |
|
D-Type Flip-Flop |
|
|
|
|
|
| Special Features |
|
|
|
Ioff,down translation to Vcc,low power,3-state |
|
|
|
|
Enable Pin |
|
|
| Bits(#) |
|
|
|
2 |
4 |
1 |
|
|
|
|
|
| Output Type |
|
|
|
|
TTL |
CMOS |
|
|
|
|
|
| Input Type |
|
|
|
|
TTL |
CMOS/TTL |
|
|
|
|
|
| Input Negative Voltage(V) |
|
|
|
|
|
|
|
|
0 |
|
|
| Input Threshold |
|
|
|
|
|
|
|
|
CMOS,TTL |
|
|
| Rise Time(ns) |
|
|
|
|
|
|
|
|
20 |
|
|
| Fall Time(ns) |
|
|
|
|
|
|
|
|
20 |
|
|
| Channel Input Logic |
|
|
|
|
|
|
|
|
Inverting |
|
|
| Prop Delay(ns) |
|
|
|
|
|
|
|
|
25 |
|
|
| Number of Channels(#) |
|
|
|
|
|
|
|
|
1 |
|
|
| Power Switch |
|
|
|
|
|
|
|
|
MOSFET,IGBT,GaNFET |
|
|
| Peak Output Current(A) |
|
|
|
|
|
|
|
|
9 |
|
|
| Input VCC(Min)(V) |
|
|
|
|
|
|
|
|
4 |
|
|
| Input VCC(Max)(V) |
|
|
|
|
|
|
|
|
15 |
|
|
| VCC Core(V) |
|
|
|
|
|
|
|
|
|
|
3.3 |
| Output Frequency(Max)(MHz) |
|
|
|
|
|
|
|
|
|
|
106.25 |
| No. of Outputs |
|
|
|
|
|
|
|
|
|
|
1 |
| VCC Out(V) |
|
|
|
|
|
|
|
|
|
|
3.3 |
| Input Level |
|
|
|
|
|
|
|
|
|
|
LVCMOS, Crystal |
| Output Level |
|
|
|
|
|
|
|
|
|
|
LVPECL |
| Output Frequency(Min)(MHz) |
|
|
|
|
|
|
|
|
|
|
106.25 |
