The LTC6954 is a family of very low phase noise clock distribution parts. Each part has three outputs and each output has an individually programmable frequency divider and delay. There are four members of the family, differing in their output logic signal type:LTC6954-1: Three LVPECL outputsLTC6954-2: Two LVPECL and one LVDS/CMOS outputsLTC6954-3: One LVPECL and two LVDS/CMOS outputsLTC6954-4: Three LVDS/CMOS outputsEach output is individually programmable to divide the input frequency by any integer from 1 to 63, and to delay each output by 0 to 63 input clock cycles. The output duty cycle is always 50%, regardless of the divide number. The LVDS/CMOS outputs are jumper selectable via the OUTxSEL pins to provide either an LVDS logic output or a CMOS logic output.The LTC6954 also features Linear Technology’s EZSync system for perfect clock synchronization and alignment every time.All device settings are controlled through an SPI-compatible serial port.Applications Clocking High Speed, High Resolution ADCs, DACs and Data Acquisition Systems Low Jitter Clock Distribution

The ADF4155 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter, external voltage controlled oscillator (VCO), and external reference frequency.The ADF4155 is for use with external VCO parts up to an 8 GHz operating frequency. The high resolution programmable modulus allows synthesis of exact frequencies with 0 Hz error.The VCO frequency can be divided by 1, 2, 4, 8, 16, 32, or 64 to allow the user to generate RF output frequencies as low as 7.8125 MHz.Control of all on-chip registers is through a simple 3-wire interface. The device operates with a nominal power supply of 3.3 V ± 5% and can be powered down when not in use.The ADF4155 is available in a 24-lead, 4 mm × 4 mm LFCSP package.APPLICATIONS Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT) Point to point/point to multipoint microwave links Test equipment Wireless LANs, CATV equipment Clock generation

The HMC877LC3 is a phase shifter/time delay with 0 to 500°(1.4 UI) continuously adjustable shift/delay range. The delay control is linearly monotonic with respect to the differential control voltage (VDCP, VDCN) and the control input has a modulation bandwidth of 2.5 GHz. The device provides a differential output voltage with constant amplitude for single-ended or differential input voltages above the input sensitivity level, while the output voltage swing may be adjusted using the VAC control pin. The HMC877LC3 features internal temperature compensation and bias circuitry to minimize delay variations with temperature. The device also features a delay control voltage range adjustment pin, LC. All RF input and outputs of the HMC877LC3 are internally terminated with 50 Ohms to VCC, and may either be AC or DC coupled. Output pins can be connected directly to a 50 Ohm to VCC terminated system, while DC blocking capacitors must be used if the terminated system input is 50 Ohms to a DC voltage other than VCC. The HMC877LC3 is available in ROHS-compliant 3 x 3 mm SMT package.APPLICATIONS Synchronization of Clock & Data Transponder Design Broadband Test & Measurement RF ATE Applications

Real Time Clock Trickle-Charge Timekeeping Chip

The ADN2915 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 6.5 Mbps to 11.3 Gbps. The ADN2915 automatically locks to all data rates without the need for an external reference clock or programming. ADN2915 jitter performance exceeds all jitter specifications required by SONET/SDH, including jitter transfer, jitter generation, and jitter tolerance.The ADN2915 provides manual or automatic slice adjust and manual sample phase adjusts. Additionally, the user can select a limiting amplifier, equalizer, or bypass at the input. The equalizer is either adaptive or can be manually set.The receiver front-end loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a user-programmable threshold. The LOS detect circuit has hysteresis to prevent chatter at the LOS output. In addition, the input signal strength can be read through the I2C registers.The ADN2915 also supports pseudorandom binary sequence (PRBS) generation, bit error detection, and input data rate readback features.The ADN2915 is available in a compact 4 mm × 4 mm, 24-lead chip scale package (LFCSP). All ADN2915 specifications are defined over the ambient temperature range of −40°C to +85°C, unless otherwise noted.Applications SONET/SDH OC-1/OC-3/OC-12/OC-48/OC-192 and all associated FEC rates 1GFC, 2GFC, 4GFC, 8GFC, 10GFC, 1GE, and 10GE WDM transponders Any rate regenerators/repeaters

Clock & Timer Development Tools LTC6993-4 Demo Board - 100ms, Falling Eg

The HMC940LC4B is a 1:4 Fanout Buffer designed to support data transmission rates up to 13 Gbps, and clock frequencies as high as 13 GHz. All differential inputs and outputs are DC coupled and terminated on chip with 50 Ohm resistors to ground. The outputs may be used in either single-ended or differential modes, and should be AC or DC coupled into 50 Ohm resistors connected to ground.The HMC940LC4B also features an output level control pin, VR which allows for loss compensation or for signal level optimization. The HMC940LC4B operates from a single -3.3V DC supply and is available in a ceramic RoHS compliant 4×4 mm SMT package.APPLICATIONS RF ATE Applications Broadband Test & Measurement Serial Data Transmission up to 13 Gbps Clock Buffering up to 13 GHz

Real Time Clock

Real Time Clock

Real Time Clock