Real Time Clock

Real Time Clock

The ADF4252 is a dual fractional-N/integer-N frequencysynthesizer that can be used to implement local oscillators (LO)in the upconversion and downconversion sections of wirelessreceivers and transmitters. Both the RF and IF synthesizersconsist of a low noise digital phase frequency detector (PFD), aprecision charge pump, and a programmable reference divider.The RF synthesizer has a ?-?-based fractional interpolator thatallows programmable fractional-N division. The IF synthesizerhas programmable integer-N counters. A complete phase-lockedloop (PLL) can be implemented if the synthesizer is used withan external loop filter and voltage controlled oscillator (VCO).Control of all the on-chip registers is via a simple 3-wire interface.The device operates with a power supply ranging from 2.7 V to3.3 V and can be powered down when not in use.Applications Base stations for mobile radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs Communications test equipment CATV equipment

The ADF4153 is a fractional-N frequency synthesizer that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a ?-? based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). In addition, the 4-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase- locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a voltage controlled oscillator (VCO).A simple 3-wire interface controls all on-chip registers. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use.Applications CATV equipment Base stations for mobile radio (GSM, PCS, DCS, WiMAX, SuperCell 3G, CDMA, W-CDMA) Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA) Wireless LANs, PMR Communications test equipment

The ADF4155 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter, external voltage controlled oscillator (VCO), and external reference frequency.The ADF4155 is for use with external VCO parts up to an 8 GHz operating frequency. The high resolution programmable modulus allows synthesis of exact frequencies with 0 Hz error.The VCO frequency can be divided by 1, 2, 4, 8, 16, 32, or 64 to allow the user to generate RF output frequencies as low as 7.8125 MHz.Control of all on-chip registers is through a simple 3-wire interface. The device operates with a nominal power supply of 3.3 V ? 5% and can be powered down when not in use.The ADF4155 is available in a 24-lead, 4 mm ? 4 mm LFCSP package.APPLICATIONS Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT) Point to point/point to multipoint microwave links Test equipment Wireless LANs, CATV equipment Clock generation

The ADF4159 is a 13 GHz, fractional-N frequency synthesizer with modulation and both fast and slow waveform generation capability. The part uses a 25-bit fixed modulus, allowing subhertz frequency resolution.The ADF4159 consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. The ?-?-based fractional interpolator allows programmable fractional-N division. The INT and FRAC registers define an overall N divider as N = INT + (FRAC/225).The ADF4159 can be used to implement frequency shift keying (FSK) and phase shift keying (PSK) modulation. Frequency sweep modes are also available to generate various waveforms in the frequency domain, for example, sawtooth and triangular waveforms. Sweeps can be set to run automatically, or each step manually triggered by an external pulse. The ADF4159 features cycle slip reduction circuitry, which enables faster lock times without the need for modifications to the loop filter.Control of all on-chip registers is via a simple 3-wire interface. The ADF4159 operates with an analog power supply in the range of 2.7 V to 3.45 V and a digital power supply in the range of 1.62 V to 1.98 V. The device can be powered down when not in use.ApplicationsCommunications infrastructureCommunications test equipmentInstrumentationFMCW radars

The ADF4377 is a high performance, ultralow jitter, dual output integer-N phased locked loop (PLL) with integrated voltage controlled oscillator (VCO) ideally suited for data converter and mixed signal front end (MxFE) clock applications. The high performance PLL has a figure of merit of -239 dBc/Hz, ultralow 1/f Noise and a high phase frequency detector (PFD) frequency that can achieve ultralow in-band noise and integrated jitter. The ADF4377?s fundamental VCO and output divider generate frequencies from 800 MHz to 12.8 GHz. The ADF4377 integrates all necessary power supply bypass capacitors, saving board space on compact boards.For multiple data converter and MxFE clock applications, the ADF4377 simplifies clock alignment and calibration routines required with other clock solutions, by implementing:automatic reference to output synchronization,extremely well match reference to output delays across process, voltage, and temperature, andsub-ps, jitter free reference to output delay adjustment capability.These features allow for predictable and precise multi-chip clock and SYSREF alignment. JESD204B and JESD204C subclass 1 solutions are supported by pairing the ADF4377 with an integrated circuit(IC) that distributes pairs of reference and SYSREF signals.APPLICATIONSHigh Performance Data Converter and MxFE ClockingWireless infrastructure (MC-GSM, 5G)Test and Measurement

The HMC911 is a broadband time delay with 62 ps to 75 pscontinuously adjustable delay range to 24 GHz. The delay controlis linearly monotonic with respect to the differential delay controlvoltage (VDCP and VDCN), and the control input has a modulationbandwidth of 1.6 Hz. The HMC911 provides a differentialoutput voltage with constant amplitude for single-ended ordifferential input voltages above the input sensitivity level, andthe output voltage swing can be adjusted using the VAC control pin.The HMC911 features internal temperature compensation andbias circuitry to minimize delay variations with temperature. AllRF inputs and outputs of the HMC911 are internally terminatedwith 50 ? to VCC and can be ac-coupled or dc-coupled. Outputpins connect directly to a 50 ? to VCC terminated system.However, use dc blocking capacitors if the terminated systeminput is 50 ? to a dc voltage other than VCC.The HMC911 is available in a RoHS-compliant, 24-terminal,ceramic, leadless chip carrier. Applications Synchronization of clock and data Transponder design Serial data transmissions up to 32 Gbps Broadband test and measurement RF ATE applications

The HMC1033LP6GE is a low-noise, wide-band 3.3 V clock generator IC with a fractional-N Phase Locked Loop (PLL) that features an integrated Voltage Controlled Oscillator (VCO). The device provides differential clock outputs between 25 MHz and 550 MHz range. The HMC1033LP6GE features a low noise Phase Detector (PD) and Delta- Sigma modulator, capable of operating at up to 100 MHz which permits wider loop-bandwidths and excellent spurious performance.The HMC1033LP6GE features industry leading phase noise and jitter performance, across the operating range, that enable it to improve link level jitter performance, Bit-Error-Rates (BER) and eye diagram metrics. The superior noise floor (<-162 dBc/Hz) makes the HMC1033LP6GE an ideal source for a variety of applications?such as clock references for high speed data converters, physical layer devices (PHY), serializer/deserializer (SER DES) circuits, FPGAs and processors. The HMC1033LP6GE can also be used as an LO for 10G/40G/100G optical modules and transponders, as well as primary reference clock for 10G/40G/100G line cards, and for jitter attenuation and frequency translation.The differential output of the HMC1033LP6GE can be set to either an LVPECL or LVDS compatible mode, with further output swing which makes the device flexible and compatible with a wide variety of signal level requirements. The output can be internally terminated to reduce component count and cost. The outputs could be terminated externally in LVPECL mode using standard methods such as resistors to ground. An Output Mute function allows the user to shut off the outputs, such as may be required for board testing or debugging. The LVPECL/LVDS, amplitude select and Output Mute function are all programmed SPI serial programming.The HMC1033LP6GE is designed to select between a Power Priority or a Performance Priority mode. The Power Priority setting reduces the current consumption of the part, whereas the Performance Priority setting improves the Jitter and Phase Noise performance.The 24 bit Delta-Sigma Modulator further enhances Hittite?s Exact Frequency Mode, which enables users to generate output frequencies with 0 Hz frequency error in many applications.APPLICATIONS 10G/40G/100G Optical Modules,?Transponders, Line Cards OTN and SONET /SDH Applications Data Converters,?Sample Clock Generation Cellular/4G Infrastructure High Frequency Processor/FPGA Clocks Any Frequency Clock Rate Generation Low Jitter SAW Oscillator Replacement DDS Replacement Frequency Translation Frequency Margining

The HMC385LP4(E) is a GaAs InGaP Heterojunction Bipolar Transistor (HBT) MMIC VCO with integrated resonator, negative resistance device, varactor diode, and buffer amplifier. Covering 2.25 to 2.5 GHz, the VCO?s phase noise performance is excellent over temperature, shock, vibration and process due to the oscillator?s monolithic structure. Power output is 4.5 dBm typical from a single supply of 3V @ 35mA. The voltage controlled oscillator is packaged in a low cost leadless QFN 4x4 mm surface mount package.APPLICATIONS Wireless Infrastructure Industrial Controls Test Equipment Military