622 Mbps Clock and Data Recovery IC

Clock Buffer 1:1 ECL, 3 Gbpps CLOCK/DATA BUFFERS

The HMC987LP5E 1-to-9 fanout buffer is designed for low noise clock distribution. It is intended to generate relatively square wave outputs with rise/fall times < 100 ps. The low skew and jitter outputs of the HMC987LP5E, combined with its fast rise/fall times, leads to controllable low-noise switching of downstream circuits such as mixers, ADCs/DACs or SERDES devices. The noise floor is particularly important in these applications, when the clocknetwork bandwidth is wide enough to allow squarewave switching. Driven at 2 GHz, outputs of the HMC987LP5E have a noise floor of –166 dBc/Hz, corresponding to a jitter density of 0.6 asec/rtHz - or 50 fs over an 8 GHz bandwidth.The input stage can be driven single-ended or differentially, in a variety of signal formats (CML, LVDS, LVPECL or CMOS), AC or DC coupled. The input stage also features adjustable input impedance. It has 8 LVPECL outputs, and 1 CML output with adjustable swing/power-level in 3 dB steps.Individual output stages may be enabled or disabled for power-savings when not required using either hardware control pins, or under control of a serial-port interface.APPLICATIONS SONET, Fibre Channel, GigE Clock Distribution ADC/DAC Clock Distribution Low Skew and Jitter Clock or Data Fanout Wireless/Wired Communications Level Translation High Performance Instrumentation Medical Imaging Single-Ended to Differential Conversion

Dual DPLL, Quad Input, 10 Output, Multiservice Line Card Clock Translator and Jitter Cleaner Features:Dual DPLL synchronizes 2 kHz to 750 MHz physical layer clocks providing frequency translation with jitter cleaning of noisy referencesComplies with ITU-T G.8262 and Telcordia GR-253Supports Telcordia GR-1244, ITU-T G.812, G.813, G.823, G.824, and G.825Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppbBoth DPLLs feature a 24-bit fractional divider with 24-bit programmable modulusProgrammable digital loop filter bandwidth: 104 Hz to 1850 HzAutomatic and manual holdover and reference switchover, providing zero delay, hitless, or phase buildout operationProgrammable priority-based reference switching with manual, automatic revertive, and automatic nonrevertive modes supported5 pairs of clock output pins with each pair useable as differential LVDS/HCSL/CML or as 2 single-ended outputs (1 Hz to 500 MHz)2 differential or 4 single-ended input referencesCrosspoint mux interconnects reference inputs to PLLsSupports embedded (modulated) input/output clock signalsFast DPLL locking modesProvides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with the frequency stability and accuracy of a TCXO or OCXOExternal EEPROM support for autonomous initializationSingle 1.8 V power supply operation with internal regulationBuilt in temperature monitor/alarm and temperature compensation for enhanced zero delay performance

Dual DPLL Digitized Clock Synchronizer Features:Digitized clock transport subsystem9 independent UTS blocks (time stamp egress ports)2 independent IUTS blocks (time stamp ingress ports)Dual DPLL synchronizes 1 Hz to 750 MHz physical layer clocks, providing frequency translation with jitter cleaning of noisy referencesComplies with ITU-T G.8262 and Telcordia GR-253Supports Telcordia GR-1244, ITU-T G.812, ITU-T G.813, ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppb (5 × 108)Both DPLLs feature a 24-bit fractional divider with 24-bit programmable modulusProgrammable digital loop filter bandwidth: 0.0001 Hz to 1850 Hz2 independent, programmable auxiliary NCOs (1 Hz to 65,535 Hz, resolution Automatic and manual holdover and reference switchover, providing zero delay, hitless, or phase buildout operationProgrammable priority-based reference switching with manual, automatic revertive, and automatic nonrevertivemodes supported5 pairs of clock output pins with each pair useable as differential LVDS/HCSL/CML or as 2 single-ended outputs (1 Hz to 500 MHz)2 differential or 8 single-ended input referencesCrosspoint mux interconnects reference inputs to PLLsSupports embedded (modulated) input/output clock signalsFast DPLL locking modesProvides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with thefrequency stability and accuracy of a TCXO or OCXOExternal EEPROM support for autonomous initializationSingle 1.8 V power supply operation with internal regulationBuilt in temperature monitor and alarm and temperature compensation for enhanced zero delay performance

Real Time Clock

Clock & Timer Development Tools LTC6992-2 Demoboard - 10kHz, 5-95 Duty

The HMC6380LC4B is a wideband MMIC VoltageControlled Oscillator which incorporates the resonator,negative resistance device, and varactor diode. Outputpower and phase noise performance are excellentover temperature due to the oscillator?s monolithicconstruction. The Vtune port accepts an analog tuningvoltage from 0 to +23V. The HMC6380LC4B VCOoperates from a single +5V supply, consumes only75 mA of current, and is housed in a RoHS compliantSMT package. This wideband VCO uniquely combinesthe attributes of ultra small size, low phase noise, lowpower consumption, and wide tuning range.Applications Industrial/Medical EquipmentMeasurement EquipmentSatcomMilitary Radar, EW, & ECM

The HMC534LP5(E) is a GaAs InGaP Heterojunction Bipolar Transistor (HBT) MMIC VCO. The HMC534LP5(E) integrates resonators, negative resistance devices, varactor diodes and feature half frequency and divide-by-4 outputs. The VCO?s phase noise performance is excellent over temperature, shock, and process due to the oscillator?s monolithic structure. Power output is +11 dBm typical from a +5V supply voltage. The prescaler and RF/2 functions can be disabled to conserve current if not required. The voltage controlled oscillator is packaged in a leadless QFN 5x5 mm surface mount package, and requires no external matching components.APPLICATIONS Point-to-Point/Multi-point Radio Test Equipment & Industrial Controls SATCOM Military End-Use

The HMC632LP5(E) is a GaAs InGaP Heterojunction Bipolar Transistor (HBT) MMIC VCO. The HMC632LP5(E) integrates resonators, negative resistance devices, varactor diodes and features half frequency and divide-by-4 outputs. The VCO?s phase noise performance is excellent over temperature, shock, and process due to the oscillator?s monolithic structure. Power output is +9 dBm typical from a +5V supply voltage. The prescaler and RF/2 functions can be disabled to conserve current if not required. The voltage controlled oscillator is packaged in a leadless QFN 5x5 mm surface mount package, and requires no external matching components.APPLICATIONS Point to Point/Multipoint Radio Test Equipment & Industrial Controls SATCOM Military End-Use