The ADF4355-2 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference frequency. A series of frequency dividers permits operation from 54 MHz to 4400 MHz. The ADF4355-2 has an integrated VCO with a fundamental output frequency ranging from 3400 MHz to 6800 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow the user to generate RF output frequencies as low as 54 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin and software controllable.Control of all on-chip registers is through a simple 3-wire interface. The ADF4355-2 operates with analog and digital power supplies ranging from 3.15 V to 3.45 V, with charge pump and VCO supplies from 4.75 V to 5.25 V. The ADF4355-2 also contains hardware and software power-down modes.Applications Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS, DECT) Point to point/point to multipoint microwave links Satellites/VSATs Test equipment/instrumentation Clock generation

The ADF4360-5 is a fully integrated integer-N synthesizer andvoltage controlled oscillator (VCO). The ADF4360-5 is designedfor a center frequency of 1300 MHz. In addition, a divide-by-2option is available, whereby the user gets an RF output ofbetween 600 MHz and 700 MHz. Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use.

The ADF4360-6 is a fully integrated integer-N synthesizerand voltage-controlled oscillator (VCO). The ADF4360-6 isdesigned for a center frequency of 1150 MHz. In addition, adivide-by-2 option is available, whereby the user receives an RFoutput of between 525 MHz and 625 MHz.Control of all the on-chip registers is through a simple 3-wireinterface. The device operates with a power supply ranging from3.0 V to 3.6 V and can be powered down when not in use.Applications Wireless handsets (DECT, GSM, PCS, DCS, WCDMA) Test equipment Wireless LANs CATV equipment

The HMC834LP6GE is a low noise, wide band, Fractional-N Phase-Locked-Loop (PLL) that features an integrated Voltage Controlled Oscillator (VCO) with a fundamental frequency of 2800 MHz - 4200 MHz, and an integrated VCO Output Divider (divide by 1/2/4/6.../60/62) and doubler, that together allow the HMC834LP6GE to generate frequencies from 45 MHz to 1050 MHz, from 1400 MHz to 2100 MHz, from 2800 MHz to 4200 MHz, and from 5600 MHz to 8400 MHz. The integrated Phase Detector (PD) and delta-sigma modulator, capable of operating at up to 100 MHz, permit wider loop-bandwidths with excellent spectral performance.The HMC834LP6GE features industry leading phase noise and spurious performance, across all frequencies, that enable it to minimize blocker effects, and improve receiver sensitivity and transmitter spectral purity. The superior noise floor (< -170 dBc/Hz) makes the HMC834LP6GE an ideal source for a variety of applications - such as; LO for RF mixers, a clock source for high-frequency data-converters, or a tunable reference source for ultra-low spurious applications.Additional features of the HMC834LP6GE include RF output power control from 0 to 6 dB (~2 dB steps), output Mute function, and a delta-sigma modulator Exact Frequency Mode which enables users to generate output frequencies with 0 Hz frequency error.Applications Cellular/4G, WiMax Infrastructure Repeaters and Femtocells Communications Test Equipment CATV Equipment Phased Array Applications DDS Replacement Very High Data Rate Radios Tunable Reference Source for?Spurious- Free Performance

The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.There are two independent clock outputs. One output is LVPECL, while the other output can be set to either LVDS or CMOS levels. The LVPECL output operates to 1.6 GHz. The other output operates to 800 MHz in LVDS mode and to 250 MHz in CMOS mode.Each output has a programmable divider that can be set to divide by a selected set of integers ranging from 1 to 32. The phase of one clock output relative to the other clock output can be set by means of a divider phase select function that serves as a coarse timing adjustment.The LVDS/CMOS output features a delay element with three selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each with 16 steps of fine adjustment.The AD9515 does not require an external controller for operation or setup. The device is programmed by means of 11 pins (S0 to S10) using 4-level logic. The programming pins are internally biased to ? VS. The VREF pin provides a level of ? VS. VS (3.3 V) and GND (0 V) provide the other two logic levels.The AD9515 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter.The AD9515 is available in a 32-lead LFCSP and operates from a single 3.3 V supply. The temperature range is ?40?C to +85?C. APPLICATIONS Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure ATE

622 Mbps Clock and Data Recovery IC

The AD9524 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz.The AD9524 is designed to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance.The input receivers, oscillator, and zero delay receiver provide both single-ended and differential operation. When connected to a recovered system reference clock and a VCXO, the device generates six low noise outputs with a range of 1 MHz to 1 GHz, and one dedicated buffered output from the input PLL (PLL1). The frequency and phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a jitter-free coarse timing adjustment in increments that are equal to one-half the period of the signal coming out of the VCO.An in-package EEPROM can be programmed through the serial interface to store user-defined register settings for power-up and chip reset.APPLICATIONS LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentation Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction (G.710) High performance wireless transceivers ATE and high performance instrumentation

The AD9837 is a low power, programmable waveform generatorcapable of producing sine, triangular, and square wave outputs.Waveform generation is required in various types of sensing,actuation, and time domain reflectometry (TDR) applications. The outputfrequency and phase are software programmable, allowing easytuning. The frequency registers are 28 bits: with a 16 MHz clock rate, resolution of 0.06 Hz can be achieved; with a 5 MHz clock rate, the AD9837can be tuned to 0.02 Hz resolution.The AD9837 is written to via a 3-wire serial interface. This serialinterface operates at clock rates up to 40 MHz and is compatiblewith DSP and microcontroller standards. The device operateswith a power supply from 2.3 V to 5.5 V.The AD9837 has a power-down (SLEEP) function. Sections of the device that are not being used can be powered down to minimize the current consumption of the part. For example, the DAC can be powered down when a clock output is being generated.The AD9837 is available in a 10-lead LFCSP_WD package.APPLICATIONS Frequency stimulus/waveform generation Liquid and gas flow measurement Sensory applications: proximity, motion, and defect detection Line loss/attenuation Test and medical equipment Sweep/clock generators Time domain reflectometry (TDR) applications

The AD9517-11 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.30 GHz to 2.65 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.The AD9517-1 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.The AD9517-1 features four LVPECL outputs (in two pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.For applications that require additional outputs, a crystal reference input, zero-delay, or EEPROM for automatic configuration at startup, the AD9520 and AD9522 are available. In addition, the AD9516 and AD9518 are similar to the AD9517 but have a different combination of outputs.Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.The AD9517-1 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).The AD9517-1 is specified for operation over the industrial range of −40°C to +85°C.Applications Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation 1AD9517 is used throughout the data sheet to refer to all the members of the AD9517 family. However, when AD9517-1 is used, it is refers to that specific member of the AD9517 family.

The AD9518-31 The AD9518-31 provides a multi-output clock distributionfunction with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.75 GHzto 2.25 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.The AD9518-3 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit otherapplications with demanding phase noise and jitter requirements.The AD9518-3 features six LVPECL outputs (in three pairs).The LVPECL outputs operate to 1.6 GHz.For applications that require additional outputs, a crystal reference input, zero-delay, or EEPROM for automatic configuration at startup, the AD9520 and AD9522 are available.In addition, the AD9516 and AD9517 are similar to the AD9518but have a different combination of outputs.Each pair of outputs has dividers that allow both the divideratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32.The AD9518-3 is available in a 48-lead LFCSP and can beoperated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).The AD9518-3 is specified for operation over the industrial range of −40°C to +85°C.Applications Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation 1AD9518 is used throughout the data sheet to refer to all the members of the AD9518 family. However, when AD9518-3 is used, it refers to that specific member of the AD9518 family.