Clock & Timer Development Tools LTC6992-3 Demo Board 0-95% Duty Cycle

Delay Lines/Timing Elements

The HMC987LP5E 1-to-9 fanout buffer is designed for low noise clock distribution. It is intended to generate relatively square wave outputs with rise/fall times < 100 ps. The low skew and jitter outputs of the HMC987LP5E, combined with its fast rise/fall times, leads to controllable low-noise switching of downstream circuits such as mixers, ADCs/DACs or SERDES devices. The noise floor is particularly important in these applications, when the clocknetwork bandwidth is wide enough to allow squarewave switching. Driven at 2 GHz, outputs of the HMC987LP5E have a noise floor of –166 dBc/Hz, corresponding to a jitter density of 0.6 asec/rtHz - or 50 fs over an 8 GHz bandwidth.The input stage can be driven single-ended or differentially, in a variety of signal formats (CML, LVDS, LVPECL or CMOS), AC or DC coupled. The input stage also features adjustable input impedance. It has 8 LVPECL outputs, and 1 CML output with adjustable swing/power-level in 3 dB steps.Individual output stages may be enabled or disabled for power-savings when not required using either hardware control pins, or under control of a serial-port interface.APPLICATIONS SONET, Fibre Channel, GigE Clock Distribution ADC/DAC Clock Distribution Low Skew and Jitter Clock or Data Fanout Wireless/Wired Communications Level Translation High Performance Instrumentation Medical Imaging Single-Ended to Differential Conversion

Clock & Timer Development Tools LTC6992-2 Demoboard - 10kHz, 5-95 Duty

Clock Drivers & Distribution LVPECL/LVECL/HSTL Clock & Data Driver

Dual DPLL, Quad Input, 10 Output, Multiservice Line Card Clock Translator and Jitter Cleaner Features:Dual DPLL synchronizes 2 kHz to 750 MHz physical layer clocks providing frequency translation with jitter cleaning of noisy referencesComplies with ITU-T G.8262 and Telcordia GR-253Supports Telcordia GR-1244, ITU-T G.812, G.813, G.823, G.824, and G.825Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppbBoth DPLLs feature a 24-bit fractional divider with 24-bit programmable modulusProgrammable digital loop filter bandwidth: 104 Hz to 1850 HzAutomatic and manual holdover and reference switchover, providing zero delay, hitless, or phase buildout operationProgrammable priority-based reference switching with manual, automatic revertive, and automatic nonrevertive modes supported5 pairs of clock output pins with each pair useable as differential LVDS/HCSL/CML or as 2 single-ended outputs (1 Hz to 500 MHz)2 differential or 4 single-ended input referencesCrosspoint mux interconnects reference inputs to PLLsSupports embedded (modulated) input/output clock signalsFast DPLL locking modesProvides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with the frequency stability and accuracy of a TCXO or OCXOExternal EEPROM support for autonomous initializationSingle 1.8 V power supply operation with internal regulationBuilt in temperature monitor/alarm and temperature compensation for enhanced zero delay performance

Microwave Wideband Synthesizer with Integrated VCO Features: RF output frequency range: 62.5 MHz to 32,000 MHz Fractional-N synthesizer and Integer N synthesizer High resolution 39-bit fractional modulus Typical spurious PFD: −90 dBc Integrated rms jitter: 38 fs (1 kHz to 100 MHz) Normalized phase noise floor: −234 dBc/Hz PFD operation to 250 MHz Reference frequency operation to 600 MHz Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output 62.5 MHz to 8,000 MHz output at RF8x and RFAUX8x 8,000 MHz to 16,000 MHz output at RF16x 16,000 MHz to 32,000 MHz output at RF32x Lock time approximately 3 ms with automatic calibration Lock time <30 μs with autocalibration bypassed Analog and digital power supplies: 3.3 V VCO power supply: 3.3 V and 5 V RF output mute function 7mm × 7mm, 48-terminal LGA package

DELAY LINE;

Clock & Timer Development Tools Network clock generator/synchronizer

TimerBlox: Voltage Controlled Silicon Oscillator Features: Fixed-Frequency or Voltage-Controlled Operation Fixed: Single Resistor Programs Frequency with <1.5% Max Error VCO: Two Resistors Set VCO Center Frequency and Tuning Range Frequency Range: 488Hz to 2MHz 2.25V to 5.5V Single Supply Operation 72µA Supply Current at 100kHz 500µs Start-Up Time VCO Bandwidth >300kHz at 1MHz CMOS Logic Output Sources/Sinks 20mA 50% Duty Cycle Square Wave Output Output Enable (Selectable Low or Hi-Z When Disabled) 55°C to 125°C Operating Temperature Range Available in Low Profile (1mm) SOT-23 (ThinSOT™) and 2mm × 3mm DFN Package AEC-Q100 Qualified for Automotive Applications