Ultralow Noise 0.37GHz to 6.39GHz Fractional-N Synthesizer with Integrated VCO Features:Low Noise Fractional-N PLL with Integrated VCONo Δ-Σ Modulator Spurs18-Bit Fractional Denominator–226 dBc/Hz Normalized In-Band Phase Noise Floor–274 dBc/Hz Normalized In-Band 1/f Noise–157 dBc/Hz Wideband Output Phase Noise FloorExcellent Integer Boundary Spurious PerformanceOutput Divider (1 to 6, 50% Duty Cycle)Output Buffer MutingReference Input Frequency Up to 425MHzFast Frequency SwitchingFracNWizard™ Software Design Tool Support

CLOCK GENERATORS & BUFFERS ROHS COMPLIANT: YES

Clock Buffer 1:2 Fanout w/+3.3V IP Pin Out

The ADN2813 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 1.25 Gb/s. The ADN2813 automatically locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to+85°C ambient temperature, unless otherwise noted.This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power fiber optic receiver.The receiver front end loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a useradjustable threshold. The LOS detect circuit has hysteresis to prevent chatter at the output.The ADN2813 is available in a compact 5 mm × 5 mm 32-lead chip scale package.ApplicationsSONET OC-1/3/12 and all associated FEC rates Fibre Channel, GbE, HDTV, etc.WDM transpondersRegenerators/repeatersTest equipmentBroadband cross-connects and routers

The AD9512 provides a multi-output clock distribution function for input signals up to 1.6 GHz. The design emphasizes low jitter and low phase noise in order to maximize data converter clocking performance. Three independent LVPECL and two LVDS clock outputs operate to 1.2 GHz and 800 MHz respectively. Optional CMOS clock outputs available to 250 MHz. Each output has a programmable divider, which may be bypassed or set to divide by any integer up to 32.Each divider allows the user to change the phase of one clock output relative to another clock output. This phase select functions as a coarse timing adjustment. One output also features a programmable delay element with a user-selected, fullscale range to 10 ns. This fine tuning delay block is programmed with a 5-bit word, which gives the user 32 possible delays from which to choose.The AD9512 is ideally suited for data converter clocking applications where maximum converter performance is achieved with sub-picosecond jitter encode signals.The AD9512 is available in a 48-lead LFCSP and is specified from -40°C to +85°C. The part may be run from a single 3.3 V supply. ApplicationsLow jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDS, DDC, DUC, MxFE™ ConvertersWireless infrastructure transceiversHigh performance instrumentationBroadband infrastructure

The AD9559 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9559 generates an output clock synchronized to up to four external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9559 continuously generates a low jitter output clock even when all reference inputs have failed.The AD9559 operates over an industrial temperature range of −40°C to +85°C. If a single DPLL version of this part is needed, refer to the AD9557.APPLICATIONS Network synchronization, including Synchronous Ethernet and OTN mapping/de-mapping Cleanup of reference clock jitter SONET/SDH clocks up to OC-192, including FEC Stratum 3 holdover, jitter cleanup, and phase transient control Wireless base station controllers Cable infrastructure Data communications

The LTC2956 is a micropower, wide input voltage range, configurable wake-up timer with pushbutton control. It periodically wakes up and turns on a connected system to perform tasks like monitoring temperature or capturing images. After completing the task, the LTC2956 turns the system off to conserve power.The wake-up timer period can be adjusted from 250ms to 39 days using configuration resistors. The system awake time can be controlled by the input pulse at the SLEEP pin or adjusted by the capacitor at the ONMAX pin. The LTC2956 operates over a wide supply input range from 1.5V to 36V. The low 800nA quiescent current suits battery powered applications.The pushbutton input allows the user to shutdown, turn on or reset the wake-up timer. With the timer in shutdown, the quiescent current drops to 300nA. The LTC2956 also provides three status outputs to indicate mode transitions and pushbutton events. Two versions are available for applications requiring either positive or negative enable polarities.Applications Heartbeat Timers Periodic Wake-Up Control Portable and Battery-Powered Equipment Intervalometers Data Acquisition

The AD9549 provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9549 generates an output clock, synchronized to one of two external input references. The external references may contain significant time jitter, also specified as phase noise. Using a digitally controlled loop and holdover circuitry, the AD9549 continues to generate a clean (low jitter), valid output clock during a loss of reference condition, even when both references have failed.The AD9549 operates over an industrial temperature range of −40°C to +85°C.APPLICATIONS Network synchronization Reference clock jitter cleanup SONET/SDH clocks up to OC-192, including FEC Stratum 3/3E reference clocks Wireless base stations, controllers Cable infrastructure Data communications

The ADF4356 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference frequency. A series of frequency dividers at another frequency output permits operation from 53.125 MHz to 6800 MHz.The ADF4356 has an integrated VCO with a fundamental output frequency ranging from 3400 MHz to 6800 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow the user to generate RF output frequencies as low as 53.125 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin- and software-controllable.Control of all on-chip registers is through a simple 3-wire interface. The ADF4356 operates with analog and digital power supplies ranging from 3.15 V to 3.45 V, with charge pump and VCO supplies from 4.75 V to 5.25 V. The ADF4356 also contains hardware and software power-down modes.Applications Wireless infrastructure (LTE, W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS) Point to point/point to multipoint microwave links Satellites/VSATs Test equipment/instrumentation Clock generation

Clock Buffer 1:2 Fanout 26GHz