The AD9554-1 is a low loop bandwidth clock translator that provides jitter cleanup and synchronization for many systems,including synchronous optical networks (SONET/SDH). The AD9554-1 generates an output clock synchronized to up to four external input references. The digital PLLs (DPLLs) allowreduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdovercircuitry of the AD9554-1 continuously generates a low jitteroutput clock even when all reference inputs have failed.The AD9554-1 operates over an industrial temperature range of ?40?C to +85?C. The AD9554 is a version of this device with two outputs per PLL. If a single or dual DPLL version of thisdevice is needed, refer to the AD9557 or AD9559, respectively.Applications Network synchronization, including synchronous Ethernet and synchronous digital hierarchy (SDH) to optical transport network (OTN) mapping/demapping Cleanup of reference clock jitter SONET/SDH clocks up to OC-192, including FEC Stratum 3 holdover, jitter cleanup, and phase transient control Cable infrastructure? Data communications? Professional video

The ADF4152HV is a 5.0 GHz, fractional-N or integer N frequency synthesizer with an integrated high voltage charge pump. The synthesizer can drive external wideband voltage controlled oscillators (VCOs) directly, eliminating the need for operational amplifiers to achieve higher tuning voltages. The integrated high voltage charge pump simplifies design and reduces cost while improving phase noise, in contrast to active filter topologies, which tend to degrade phase noise compared to passive filter topologies.The VCO frequency can be divided by 1, 2, 4, 8, or 16 to allow the user to generate RF output frequencies as low as 31.25 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin and software controllable.A simple 3-wire interface controls all on-chip registers. The charge pump operates from a power supply ranging from 6.0 V to 30 V, whereas the rest of the device operates from 3.0 V to 3.6 V. The ADF4152HV can be powered down when not in use.Applications Wireless infrastructure Microwave point to point/point to multipoint radios Very small aperture terminal (VSAT) radios Test equipment Private land mobile radios

Real Time Clock

Delay Lines/Timing Elements

The AD9522-31 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.72 GHz to 2.25 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used. The AD9522 serial interface supports both SPI and I2C® ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset.The AD9522 features 12 LVDS outputs in four groups. Any of the 800 MHz LVDS outputs can be reconfigured as two 250 MHz CMOS outputs.Each group of outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase (coarse delay) to be set. The AD9522 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage up to 5.5 V. The AD9522 is specified for operation over the standard industrialrange of −40°C to +85°C.The AD9520-3 is an equivalent part to the AD9522-3 featuringLVPECL / CMOS drivers instead of LVDS / CMOS drivers.1The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-3 is used, it is referring to that specificmember of the AD9522 family.ApplicationsLow jitter, low phase noise clock distributionClock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocolsForward error correction (G.710)Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEsHigh performance wireless transceiversATE and high performance instrumentationBroadband infrastructuresData Sheet, Rev. 0, 10/08

Timers & Support Products Low-Power General Purpose Timer

Delay Lines/Timing Elements

Real Time Clock

Continuous Rate 10 Mb/s to 675 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp Features: Serial data input: 10 Mb/s to 675 Mb/s Exceeds SONET requirements for jitter transfer/generation/tolerance Quantizer sensitivity: 3.3 mV typical Adjustable slice level: ±95 mV Patented clock recovery architecture Loss-of-signal (LOS) detect range: 2.3 mV to 19 mV Independent slice level adjust and LOS detector No reference clock required Loss-of-lock indicator I2C™ interface to access optional features Single-supply operation: 3.3 V Low power: 435 mW typical 5 mm × 5 mm, 32-lead LFCSP, Pb free

The ADN2813 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 1.25 Gb/s. The ADN2813 automatically locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to+85°C ambient temperature, unless otherwise noted.This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power fiber optic receiver.The receiver front end loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a useradjustable threshold. The LOS detect circuit has hysteresis to prevent chatter at the output.The ADN2813 is available in a compact 5 mm × 5 mm 32-lead chip scale package.ApplicationsSONET OC-1/3/12 and all associated FEC rates Fibre Channel, GbE, HDTV, etc.WDM transpondersRegenerators/repeatersTest equipmentBroadband cross-connects and routers