The HMC840LP6CE is a fully functioned Fractional-N Phase-Locked-Loop (PLL) Frequency Synthesizer with an Integrated Voltage Controlled Oscillator (VCO). The synthesizer consists of an integrated low noise VCO with a triband output, an autocalibration subsystem for low voltage VCO tuning, a very low noise digital Phase Detector (PD), a precision controlled charge pump, a low noise reference path divider and a fractional divider.The fractional synthesizer features an advanced delta-sigma modulator design that allows both ultra-fine step sizes and low spurious products. The phase detector (PD) features cycle slip prevention (CSP) technology to allow faster frequency hopping times. Ultra low in-close phase noise and low spurious also allows wider loop bandwidths for faster frequency hopping and low micro-phonics.For theory of operation and register map refer to the 'PLLs with Integrated VCO - RF VCOs' Operating Guide.Applications Cellular/4G Infrastructure Repeaters & Femtocells Communications?Test Equipment CATV Equipment Phased Array Applications DDS Replacement? Very High Data Rate Radios

The AD9572 provides a multioutput clock generator function along with two on-chip PLL cores, optimized for fiber channel line card applications that include an Ethernet interface. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequencysynthesizers to maximize network performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. The PLL section consists of a low noise phase frequency detector (PFD), a precision charge pump (CP), a low phase noise voltage controlled oscillator (VCO), and a preprogrammed feedback divider and output divider. By connecting an external crystal or reference clock to the REFCLK pin, frequencies up to 156.25 MHz can be locked to the input reference. Each output divider and feedback divider ratio is preprogrammed for therequired output rates. A second PLL also operates as an integer-N synthesizer anddrives two LVPECL or LVDS output buffers for 106.25 MHzoperation. No external loop filter components are required, thusconserving valuable design time and board space. The AD9572 is available in a 40-lead, 6 mm ? 6 mm lead framechip scale package (LFCSP) and can be operated from a single3.3 V supply. The temperature range is ?40?C to +85?C.APPLICATIONSFiber channel line cards, switches, and routersGigabit Ethernet/PCIe support included Low jitter, low phase noise clock generation

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LMX2531 High Performance Frequency Synthesizer System with Integrated VCO

The ADF4196 frequency synthesizer can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture isspecifically designed to meet the GSM/EDGE lock time requirements for base stations, and the fast settling feature makes theADF4196 suitable for pulse Doppler radar applications.The ADF4196 consists of a low noise, digital phase frequency detector (PFD) and a precision differential charge pump. A differential amplifier converts the differential charge pump output to a single-ended voltage for the external voltage controlled oscillator (VCO). The sigma-delta (?-?) based fractional interpolator, working with the N divider, allows programmable modulus fractional-N division. Additionally, the 4-bit reference (R) counter and on-chip frequency doubler allow selectable reference signal (REFIN) frequencies at the PFD input.A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles within the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases the cost, complexity, PCB area, shielding, and characterization found on previous ping-pong GSM PLL architectures.Applications GSM/EDGE base stations PHS base stations Pulsed Doppler radar Instrumentation and test equipment Beam-forming/phased array systems

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