CLOCK GENERATORS & BUFFERS ROHS COMPLIANT: YES

Ultralow Noise 0.35GHz to 6GHz Fractional-N Synthesizer Features:Low Noise Fractional-N PLLNo ΔΣ Modulator Spurs18-Bit Fractional Denominator350MHz to 6GHz VCO Input Range–226dBc/Hz Normalized In-Band Phase Noise Floor–274dBc/Hz Normalized In-Band 1/f Noise–157dBc/Hz Wideband Output Phase Noise FloorExcellent Integer Boundary Spurious PerformanceOutput Divider (1 to 6, 50% Duty Cycle)Output Buffer MutingCharge Pump Supply from 3.15V to 5.25VCharge Pump Current from 1mA to 11.2mAReference Input Frequency Up to 425MHzFast Frequency Switching

Ultralow Noise 0.37GHz to 6.39GHz Fractional-N Synthesizer with Integrated VCO Features:Low Noise Fractional-N PLL with Integrated VCONo Δ-Σ Modulator Spurs18-Bit Fractional Denominator–226 dBc/Hz Normalized In-Band Phase Noise Floor–274 dBc/Hz Normalized In-Band 1/f Noise–157 dBc/Hz Wideband Output Phase Noise FloorExcellent Integer Boundary Spurious PerformanceOutput Divider (1 to 6, 50% Duty Cycle)Output Buffer MutingReference Input Frequency Up to 425MHzFast Frequency SwitchingFracNWizard™ Software Design Tool Support

TimerBlox: Voltage Controlled Silicon Oscillator Features: Fixed-Frequency or Voltage-Controlled Operation Fixed: Single Resistor Programs Frequency with <1.5% Max Error VCO: Two Resistors Set VCO Center Frequency and Tuning Range Frequency Range: 488Hz to 2MHz 2.25V to 5.5V Single Supply Operation 72µA Supply Current at 100kHz 500µs Start-Up Time VCO Bandwidth >300kHz at 1MHz CMOS Logic Output Sources/Sinks 20mA 50% Duty Cycle Square Wave Output Output Enable (Selectable Low or Hi-Z When Disabled) 55°C to 125°C Operating Temperature Range Available in Low Profile (1mm) SOT-23 (ThinSOT™) and 2mm × 3mm DFN Package AEC-Q100 Qualified for Automotive Applications

Microwave Wideband Synthesizer with Integrated VCO Features: RF output frequency range: 62.5 MHz to 32,000 MHz Fractional-N synthesizer and Integer N synthesizer High resolution 39-bit fractional modulus Typical spurious PFD: −90 dBc Integrated rms jitter: 38 fs (1 kHz to 100 MHz) Normalized phase noise floor: −234 dBc/Hz PFD operation to 250 MHz Reference frequency operation to 600 MHz Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output 62.5 MHz to 8,000 MHz output at RF8x and RFAUX8x 8,000 MHz to 16,000 MHz output at RF16x 16,000 MHz to 32,000 MHz output at RF32x Lock time approximately 3 ms with automatic calibration Lock time <30 μs with autocalibration bypassed Analog and digital power supplies: 3.3 V VCO power supply: 3.3 V and 5 V RF output mute function 7mm × 7mm, 48-terminal LGA package

Broadband Analog Time Delay SMT, DC - 24 GHz Features: Very Wide Bandwidth: DC - 24 GHz Continuous Adjustable Delay Range: 70 ps Single-Ended or Differential Operation Adjustable Differential Output Voltage Swing: 170 - 760 mVp-p @ 24 GHz Delay Control Modulation Bandwidth: 10 MHz Single Supply: +3.3V  24 Lead 4x4mm SMT Package: 16mm²

Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B / JESD204C Support Features: JESD204B/C, Subclass 1 SYSREF Signal Generation Low Noise Integer-N PLL Additive Output Jitter < 6fsRMS (Integration BW = 12kHz to 20MHz, f = 4.5GHz) Additive Output Jitter 65fsRMS (ADC SNR Method) EZSync™, ParallelSync™ Multichip Synchronization –229dBc/Hz Normalized In-Band Phase Noise Floor –281dBc/Hz Normalized In-Band 1/f Noise Eleven Independent, Low Noise Outputs with Programmable Coarse Digital and Fine Analog Delays Flexible Outputs Can Serve as Either a Device Clock or SYSREF Signal Reference Input Frequency up to 500MHz LTC6952Wizard™ Software Design Tool Support –40ºC to 125°C Operating Junction Temperature Range

EVALUATION BOARD PLL CLOCK SYNTHESIZER; Silicon Manufacturer:Analog Devices; Silicon Core Number:AD9520-0; Kit Application Type:Clock & Timing; Application Sub Type:PLL Clock Synthesizer; Kit Contents:Eval Board AD9520 ;RoHS Compliant: Yes

The AD9517-31 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.75 GHz to 2.25 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.The AD9517-3 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.The AD9517-3 features four LVPECL outputs (in two pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.For applications that require additional outputs, a crystal reference input, zero-delay, or EEPROM for automatic configuration at startup, the AD9520 and AD9522 are available. In addition, the AD9516 and AD9518 are similar to the AD9517 but have a different combination of outputs.Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.The AD9517-3 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).The AD9517-3 is specified for operation over the industrial range of ?40?C to +85?C.APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation 1 AD9517 is used throughout to refer to all the members of the AD9517 family. However, when AD9517-3 is used, it is referring to that specific member of the AD9517 family.

The AD9554-1 is a low loop bandwidth clock translator that provides jitter cleanup and synchronization for many systems,including synchronous optical networks (SONET/SDH). The AD9554-1 generates an output clock synchronized to up to four external input references. The digital PLLs (DPLLs) allowreduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdovercircuitry of the AD9554-1 continuously generates a low jitteroutput clock even when all reference inputs have failed.The AD9554-1 operates over an industrial temperature range of ?40?C to +85?C. The AD9554 is a version of this device with two outputs per PLL. If a single or dual DPLL version of thisdevice is needed, refer to the AD9557 or AD9559, respectively.Applications Network synchronization, including synchronous Ethernet and synchronous digital hierarchy (SDH) to optical transport network (OTN) mapping/demapping Cleanup of reference clock jitter SONET/SDH clocks up to OC-192, including FEC Stratum 3 holdover, jitter cleanup, and phase transient control Cable infrastructure? Data communications? Professional video