Broadband Analog Time Delay SMT, DC - 24 GHz Features: Very Wide Bandwidth: DC - 24 GHz Continuous Adjustable Delay Range: 70 ps Single-Ended or Differential Operation Adjustable Differential Output Voltage Swing: 170 - 760 mVp-p @ 24 GHz Delay Control Modulation Bandwidth: 10 MHz Single Supply: +3.3V  24 Lead 4x4mm SMT Package: 16mm²

Dual DPLL, Quad Input, 10 Output, Multiservice Line Card Clock Translator and Jitter Cleaner Features:Dual DPLL synchronizes 2 kHz to 750 MHz physical layer clocks providing frequency translation with jitter cleaning of noisy referencesComplies with ITU-T G.8262 and Telcordia GR-253Supports Telcordia GR-1244, ITU-T G.812, G.813, G.823, G.824, and G.825Continuous frequency monitoring and reference validation for frequency deviation as low as 50 ppbBoth DPLLs feature a 24-bit fractional divider with 24-bit programmable modulusProgrammable digital loop filter bandwidth: 104 Hz to 1850 HzAutomatic and manual holdover and reference switchover, providing zero delay, hitless, or phase buildout operationProgrammable priority-based reference switching with manual, automatic revertive, and automatic nonrevertive modes supported5 pairs of clock output pins with each pair useable as differential LVDS/HCSL/CML or as 2 single-ended outputs (1 Hz to 500 MHz)2 differential or 4 single-ended input referencesCrosspoint mux interconnects reference inputs to PLLsSupports embedded (modulated) input/output clock signalsFast DPLL locking modesProvides internal capability to combine the low phase noise of a crystal resonator or crystal oscillator with the frequency stability and accuracy of a TCXO or OCXOExternal EEPROM support for autonomous initializationSingle 1.8 V power supply operation with internal regulationBuilt in temperature monitor/alarm and temperature compensation for enhanced zero delay performance

Ultralow Noise 0.35GHz to 6GHz Fractional-N Synthesizer Features:Low Noise Fractional-N PLLNo ΔΣ Modulator Spurs18-Bit Fractional Denominator350MHz to 6GHz VCO Input Range–226dBc/Hz Normalized In-Band Phase Noise Floor–274dBc/Hz Normalized In-Band 1/f Noise–157dBc/Hz Wideband Output Phase Noise FloorExcellent Integer Boundary Spurious PerformanceOutput Divider (1 to 6, 50% Duty Cycle)Output Buffer MutingCharge Pump Supply from 3.15V to 5.25VCharge Pump Current from 1mA to 11.2mAReference Input Frequency Up to 425MHzFast Frequency Switching

Ultralow Noise 0.37GHz to 6.39GHz Fractional-N Synthesizer with Integrated VCO Features:Low Noise Fractional-N PLL with Integrated VCONo Δ-Σ Modulator Spurs18-Bit Fractional Denominator–226 dBc/Hz Normalized In-Band Phase Noise Floor–274 dBc/Hz Normalized In-Band 1/f Noise–157 dBc/Hz Wideband Output Phase Noise FloorExcellent Integer Boundary Spurious PerformanceOutput Divider (1 to 6, 50% Duty Cycle)Output Buffer MutingReference Input Frequency Up to 425MHzFast Frequency SwitchingFracNWizard™ Software Design Tool Support

VCO with Divide-by-4, 8.6 - 10.2 GHz Features: Dual Output: Fo = 8.6 - 10.2 GHz Fo/4 = 2.15 - 2.55 GHz Pout: +18 dBm Phase Noise: -100 dBc/Hz @ 100 kHz Typ. No External Resonator Needed 32 Lead 5×5 mm QFN Package: 25 mm2

Delay Lines/Timing Elements 5-Tap Timing Element

Delay Lines/Timing Elements

The ADCLK914 is an ultrafast clock/data buffer fabricated onthe Analog Devices, Inc., proprietary, complementary bipolar(XFCB-3) silicon-germanium (SiGe) process. The ADCLK914features high voltage differential signaling (HVDS) outputssuitable for driving the latest Analog Devices high speed digitalto-analogconverters (DACs). The ADCLK914 has a single,differential open-collector output.The ADCLK914 buffer operates up to 7.5 GHz with a 160 pspropagation delay and adds only 110 fs random jitter (RJ).The input has a center tapped, 100 Ω, on-chip terminationresistor and accepts LVPECL, CML, CMOS, LVTTL, or LVDS(ac-coupled only). A VREF pin is available for biasing ac-coupledinputs.The HVDS output stage is designed to directly drive 1.9 V eachside into 50 Ω terminated to VCC for a total differential outputswing of 3.8 V.The ADCLK914 is available in a 16-lead LFCSP. It is specifiedfor operation over the extended industrial temperature range of−40°C to +125°C.Applications Clock and data signal restoration High speed converter clocking Broadband communications Cellular infrastructure High speed line receivers ATE and high performance instrumentation Level shifting Threshold detection 

The ADCLK905 (one input, one output), ADCLK907 (dual oneinput, one output), and ADCLK925 (one input, two outputs) areultrafast clock/data buffers fabricated on the Analog Devices, Inc.,proprietary XFCB3 silicon germanium (SiGe) bipolar process.The ADCLK905/ADCLK907/ADCLK925 feature full-swing emitter coupled logic (ECL) output drivers. For PECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For NECL (negative ECL) operation, bias VCC to ground and VEE to the negative supply.The buffers offer 95 ps propagation delay, 7.5 GHz toggle rate, 10 Gbps data rate, and 60 fs random jitter (RJ).The inputs have center tapped, 100 Ω, on-chip termination resistors. A VREF pin is available for biasing ac-coupled inputs.The ECL output stages are designed to directly drive 800 mV each side into 50 Ω terminated to VCC − 2 V for a total differential output swing of 1.6 V.The ADCLK905/ADCLK907/ADCLK925 are available in 16-lead LFCSP packages.Applications Clock and data signal restoration and level shifting Automated test equipment (ATE) High speed instrumentation High speed line receivers Threshold detection Converter clocking

The HMC704 has been designed for the best phase noise and lowest spurious content possible in an integrated synthesizer. Fabricated in a SiGe BiCMOS process, this Fractional-N frequency synthesizer consists of a very low noise digital phase detector, VCO divider, reference divider and a precision controlled charge pump.Ultra low in-close phase noise and low spurious allows wide loop bandwidths for faster frequency hopping and low micro-phonics. Exact frequency mode with 24-bit fractional modulator provides the ability to generate fractional frequencies with zero frequency error, an important feature for Digital Pre-Distortion systems.The serial interface offers read back capability and is compatible with a wide variety of protocols.Applications Microwave Point-to-Point Radios  Base Stations for Mobile Radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs, WiMAX Communications Test Equipment CATV Equipment Automotive