The HMC834LP6GE is a low noise, wide band, Fractional-N Phase-Locked-Loop (PLL) that features an integrated Voltage Controlled Oscillator (VCO) with a fundamental frequency of 2800 MHz - 4200 MHz, and an integrated VCO Output Divider (divide by 1/2/4/6.../60/62) and doubler, that together allow the HMC834LP6GE to generate frequencies from 45 MHz to 1050 MHz, from 1400 MHz to 2100 MHz, from 2800 MHz to 4200 MHz, and from 5600 MHz to 8400 MHz. The integrated Phase Detector (PD) and delta-sigma modulator, capable of operating at up to 100 MHz, permit wider loop-bandwidths with excellent spectral performance.The HMC834LP6GE features industry leading phase noise and spurious performance, across all frequencies, that enable it to minimize blocker effects, and improve receiver sensitivity and transmitter spectral purity. The superior noise floor (< -170 dBc/Hz) makes the HMC834LP6GE an ideal source for a variety of applications - such as; LO for RF mixers, a clock source for high-frequency data-converters, or a tunable reference source for ultra-low spurious applications.Additional features of the HMC834LP6GE include RF output power control from 0 to 6 dB (~2 dB steps), output Mute function, and a delta-sigma modulator Exact Frequency Mode which enables users to generate output frequencies with 0 Hz frequency error.Applications Cellular/4G, WiMax Infrastructure Repeaters and Femtocells Communications Test Equipment CATV Equipment Phased Array Applications DDS Replacement Very High Data Rate Radios Tunable Reference Source for?Spurious- Free Performance

The HMC987LP5E 1-to-9 fanout buffer is designed for low noise clock distribution. It is intended to generate relatively square wave outputs with rise/fall times < 100 ps. The low skew and jitter outputs of the HMC987LP5E, combined with its fast rise/fall times, leads to controllable low-noise switching of downstream circuits such as mixers, ADCs/DACs or SERDES devices. The noise floor is particularly important in these applications, when the clocknetwork bandwidth is wide enough to allow squarewave switching. Driven at 2 GHz, outputs of the HMC987LP5E have a noise floor of ?166 dBc/Hz, corresponding to a jitter density of 0.6 asec/rtHz - or 50 fs over an 8 GHz bandwidth.The input stage can be driven single-ended or differentially, in a variety of signal formats (CML, LVDS, LVPECL or CMOS), AC or DC coupled. The input stage also features adjustable input impedance. It has 8 LVPECL outputs, and 1 CML output with adjustable swing/power-level in 3 dB steps.Individual output stages may be enabled or disabled for power-savings when not required using either hardware control pins, or under control of a serial-port interface.APPLICATIONS SONET, Fibre Channel,?GigE Clock Distribution ADC/DAC Clock Distribution Low Skew and Jitter Clock?or Data Fanout Wireless/Wired Communications Level Translation High Performance Instrumentation Medical Imaging Single-Ended to Differential?Conversion

The HMC1161 is a monolithic microwave integrated circuit (MMIC), voltage controlled oscillator (VCO) that integrates a resonator, a negative resistance device, and a varactor diode, and features a half frequency output. Because of the monolithic construction of the oscillator, the output power and phase noise performance are excellent over temperature.The output power is 11 dBm typical from a 5 V supply voltage. The VCO is housed in a RoHS-compliant LFCSP and requires no external matching components.Applications Point to point and multipoint radios? Test equipment and industrial controls? Very small aperture terminals (VSATs)?

The LTC6951 is a high performance, low noise, Phase Locked Loop (PLL) with a fully integrated VCO. The low noise VCO uses no external components and is internally calibrated to the correct output frequency with no external system support.The clock generation section provides five outputs based on the VCO prescaler signal with individual dividers for each output. Four outputs feature very low noise, low skew CML logic. The fifth output is low noise LVDS. All outputs can be synchronized and set to precise phase alignment using the programmable delays.Choose the LTC6951-1 if any desired output frequency falls in the ranges 2.5GHz to 2.7GHz, 1.66GHz to 1.8GHz, or 1.25GHz to 1.35GHz. Choose the LTC6951 for all other frequencies.Applications High Performance Data Converter Clocking Wireless Infrastructure Test and Measurement

The ADF4152HV is a 5.0 GHz, fractional-N or integer N frequency synthesizer with an integrated high voltage charge pump. The synthesizer can drive external wideband voltage controlled oscillators (VCOs) directly, eliminating the need for operational amplifiers to achieve higher tuning voltages. The integrated high voltage charge pump simplifies design and reduces cost while improving phase noise, in contrast to active filter topologies, which tend to degrade phase noise compared to passive filter topologies.The VCO frequency can be divided by 1, 2, 4, 8, or 16 to allow the user to generate RF output frequencies as low as 31.25 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin and software controllable.A simple 3-wire interface controls all on-chip registers. The charge pump operates from a power supply ranging from 6.0 V to 30 V, whereas the rest of the device operates from 3.0 V to 3.6 V. The ADF4152HV can be powered down when not in use.Applications Wireless infrastructure Microwave point to point/point to multipoint radios Very small aperture terminal (VSAT) radios Test equipment Private land mobile radios

The AD9517-31 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.75 GHz to 2.25 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.The AD9517-3 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.The AD9517-3 features four LVPECL outputs (in two pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.For applications that require additional outputs, a crystal reference input, zero-delay, or EEPROM for automatic configuration at startup, the AD9520 and AD9522 are available. In addition, the AD9516 and AD9518 are similar to the AD9517 but have a different combination of outputs.Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.The AD9517-3 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).The AD9517-3 is specified for operation over the industrial range of ?40?C to +85?C.APPLICATIONS Low jitter, low phase noise clock distribution 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4 Forward error correction (G.710) Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers ATE and high performance instrumentation 1 AD9517 is used throughout to refer to all the members of the AD9517 family. However, when AD9517-3 is used, it is referring to that specific member of the AD9517 family.

The AD9554-1 is a low loop bandwidth clock translator that provides jitter cleanup and synchronization for many systems,including synchronous optical networks (SONET/SDH). The AD9554-1 generates an output clock synchronized to up to four external input references. The digital PLLs (DPLLs) allowreduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdovercircuitry of the AD9554-1 continuously generates a low jitteroutput clock even when all reference inputs have failed.The AD9554-1 operates over an industrial temperature range of ?40?C to +85?C. The AD9554 is a version of this device with two outputs per PLL. If a single or dual DPLL version of thisdevice is needed, refer to the AD9557 or AD9559, respectively.Applications Network synchronization, including synchronous Ethernet and synchronous digital hierarchy (SDH) to optical transport network (OTN) mapping/demapping Cleanup of reference clock jitter SONET/SDH clocks up to OC-192, including FEC Stratum 3 holdover, jitter cleanup, and phase transient control Cable infrastructure? Data communications? Professional video

The AD-SYNCHRONA14-EBZ is an ideal self-contained device to use in evaluation and prototyping of applications that need a highly accurate frequency and phase-controlled source clock. It is designed around the Analog Devices AD9545 and HMC7044 and greatly simplifies clock distribution and multi-channel synchronization in complex systems. It is intended to be used by trained professionals in a laboratory environment, and not intended as an end product for commercial use. It can be taken as a complete reference design and customised as required for any end customer applications. Full design details are made available free of charge.

The AD-SYNCHRONA14-EBZ comes in a 1U mechanical form factor. Using popular industry connector SMA and TwinAX interfaces most labs will already have the needed cables.

With its internal OCXO it can operate in standalone mode or be fed from a choice of external sources, such as 3 separate high speed differential clock inputs, a 10MHz reference and 1PPS. This flexibility combined with the capability to select either of the internal VCXO options of 100MHz or 122.88MHz, gives almost unlimited choice for the frequency of interest and accuracy needed for a wide variety of application areas. 

Real Time Clock

Continuous Rate 10 Mb/s to 675 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp Features: Serial data input: 10 Mb/s to 675 Mb/s Exceeds SONET requirements for jitter transfer/generation/tolerance Quantizer sensitivity: 3.3 mV typical Adjustable slice level: ±95 mV Patented clock recovery architecture Loss-of-signal (LOS) detect range: 2.3 mV to 19 mV Independent slice level adjust and LOS detector No reference clock required Loss-of-lock indicator I2C™ interface to access optional features Single-supply operation: 3.3 V Low power: 435 mW typical 5 mm × 5 mm, 32-lead LFCSP, Pb free