The AD9512 provides a multi-output clock distribution function for input signals up to 1.6 GHz. The design emphasizes low jitter and low phase noise in order to maximize data converter clocking performance. Three independent LVPECL and two LVDS clock outputs operate to 1.2 GHz and 800 MHz respectively. Optional CMOS clock outputs available to 250 MHz. Each output has a programmable divider, which may be bypassed or set to divide by any integer up to 32.Each divider allows the user to change the phase of one clock output relative to another clock output. This phase select functions as a coarse timing adjustment. One output also features a programmable delay element with a user-selected, fullscale range to 10 ns. This fine tuning delay block is programmed with a 5-bit word, which gives the user 32 possible delays from which to choose.The AD9512 is ideally suited for data converter clocking applications where maximum converter performance is achieved with sub-picosecond jitter encode signals.The AD9512 is available in a 48-lead LFCSP and is specified from -40°C to +85°C. The part may be run from a single 3.3 V supply. ApplicationsLow jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDS, DDC, DUC, MxFE™ ConvertersWireless infrastructure transceiversHigh performance instrumentationBroadband infrastructure

The HMC704 has been designed for the best phase noise and lowest spurious content possible in an integrated synthesizer. Fabricated in a SiGe BiCMOS process, this Fractional-N frequency synthesizer consists of a very low noise digital phase detector, VCO divider, reference divider and a precision controlled charge pump.Ultra low in-close phase noise and low spurious allows wide loop bandwidths for faster frequency hopping and low micro-phonics. Exact frequency mode with 24-bit fractional modulator provides the ability to generate fractional frequencies with zero frequency error, an important feature for Digital Pre-Distortion systems.The serial interface offers read back capability and is compatible with a wide variety of protocols.Applications Microwave Point-to-Point Radios  Base Stations for Mobile Radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs, WiMAX Communications Test Equipment CATV Equipment Automotive

Delay Lines/Timing Elements

Delay Lines/Timing Elements

Clock & Timer Development Tools Clock Divider board

Real Time Clock

PLL CLOCK SYNTHESIZER GUI EVALUATION BOARD; Silicon Manufacturer:Analog Devices; Silicon Core Number:AD9520; Kit Application Type:Clock & Timing; Application Sub Type:PLL Clock Synthesizer; Kit Contents:Eval Board AD9520-1 ;RoHS Compliant: Yes

DIFF FANOUT BUFFER 2:8 DIFF LFCSP-28; Logic Family / Base Number:-; Logic Device Type:Fanout Buffer; Logic Case Style:LFCSP; No. of Pins:28Pins; Supply Voltage Min:2.375V; Supply Voltage Max:2.625V; Logic IC Family:-; Logic IC Base;RoHS Compliant: Yes

The AD9552 is a fractional-N phase locked loop (PLL) based clock generator designed specifically to replace high frequency crystal oscillators and resonators. The device employs a sigma-delta (Σ-Δ) modulator (SDM) to accommodate fractional frequency synthesis. The user supplies an input reference signal by connecting a single-ended clock signal directly to the REF pin or by connecting a crystal resonator across the XTAL pins.The AD9552 is pin programmable, providing one of 64 standard output frequencies based on one of eight common input frequencies. The device also has a 3-wire SPI interface, enabling the user to program custom input-to-output frequency ratios.The AD9552 relies on an external capacitor to complete the loop filter of the PLL. The output is compatible with LVPECL, LVDS, or single-ended CMOS logic levels, although the AD9552 is implemented in a strictly CMOS process.The AD9552 is specified to operate over the extended industrial temperature range of −40°C to +85°C.APPLICATIONS Cost effective replacement of high frequency VCXO, OCXO, and SAW resonators Extremely flexible frequency translation with low jitter for SONET/SDH (including FEC) , 10 Gb Ethernet, Fibre Channel, and DRFI/DOCSIS High-definition video frequency translation Wireless infrastructure Test and measurement (including handheld devices)

The ADCLK946 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter.The device has a differential input equipped with center-tapped, differential, 100 Ω on-chip termination resistors. The input accepts dc-coupled LVPECL, CML, 3.3 V CMOS (single ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREF pin is available for biasing ac-coupled inputs.The ADCLK946 features six full-swing emitter-coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply.The ECL output stages are designed to directly drive 800 mV each side into 50 Ω terminated to VCC − 2 V for a total differen-tial output swing of 1.6 V.The ADCLK946 is available in a 24-lead LFCSP and is specified for operation over the standard industrial temperature range of −40°C to +85°C.ApplicationsLow jitter clock distributionClock and data signal restorationLevel translationWireless communicationsWired communicationsMedical and industrial imagingATE and high performance instrumentation