The HMC703 fractional synthesizer is built upon the high performance PLL platform also contained in the HMC704 and Hittite?s latest generation of PLL+VCO products. This platform has the best phase-noise and spurious performance in the industry - enabling higher order modulation schemes while minimizing blocker effects in high performance radios.In addition, the HMC703 offers frequency sweep and modulation features, external triggering, double-buffering, exact frequency control, phase modulation and more - while maintaining pin compatibility for the main functions with the HMC700.Applications Microwave Point-to-Point Radios? Base Stations for Mobile Radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs, WiMAX Communications Test Equipment ATV Equipment Automotive Sensors AESA - Phased Arrays FMCW Radar Systems

Real Time Clock

Real Time Clock

Real Time Clock

The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs.The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be used with an external VCO or VCXO. The VCO input and eight LVPECL outputs can operate up to a frequency of 3.6 GHz. All outputs share a common divider that can provide a division of 1 to 6.The AD9525 offers a dedicated output that can be used to provide a programmable signal for resetting or synchronizing a data converter. The output signal is activated by a SPI write.The AD9525 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. The external VCXO or VCO can have an operating voltage of up to 5.5 V.The AD9525 operates over the extended industrial temperature range of −40°C to +85°C.Applications LTE and multicarrier GSM base stations Clocking high speed ADCs, DACs ATE and high performance instrumentation 40/100Gb/s OTN Line Side Clocking Cable/DOCSIS CMTS Clocking Test and Measurement

The AD9512 provides a multi-output clock distribution function for input signals up to 1.6 GHz. The design emphasizes low jitter and low phase noise in order to maximize data converter clocking performance. Three independent LVPECL and two LVDS clock outputs operate to 1.2 GHz and 800 MHz respectively. Optional CMOS clock outputs available to 250 MHz. Each output has a programmable divider, which may be bypassed or set to divide by any integer up to 32.Each divider allows the user to change the phase of one clock output relative to another clock output. This phase select functions as a coarse timing adjustment. One output also features a programmable delay element with a user-selected, fullscale range to 10 ns. This fine tuning delay block is programmed with a 5-bit word, which gives the user 32 possible delays from which to choose.The AD9512 is ideally suited for data converter clocking applications where maximum converter performance is achieved with sub-picosecond jitter encode signals.The AD9512 is available in a 48-lead LFCSP and is specified from -40°C to +85°C. The part may be run from a single 3.3 V supply. ApplicationsLow jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDS, DDC, DUC, MxFE™ ConvertersWireless infrastructure transceiversHigh performance instrumentationBroadband infrastructure

The AD9552 is a fractional-N phase locked loop (PLL) based clock generator designed specifically to replace high frequency crystal oscillators and resonators. The device employs a sigma-delta (Σ-Δ) modulator (SDM) to accommodate fractional frequency synthesis. The user supplies an input reference signal by connecting a single-ended clock signal directly to the REF pin or by connecting a crystal resonator across the XTAL pins.The AD9552 is pin programmable, providing one of 64 standard output frequencies based on one of eight common input frequencies. The device also has a 3-wire SPI interface, enabling the user to program custom input-to-output frequency ratios.The AD9552 relies on an external capacitor to complete the loop filter of the PLL. The output is compatible with LVPECL, LVDS, or single-ended CMOS logic levels, although the AD9552 is implemented in a strictly CMOS process.The AD9552 is specified to operate over the extended industrial temperature range of −40°C to +85°C.APPLICATIONS Cost effective replacement of high frequency VCXO, OCXO, and SAW resonators Extremely flexible frequency translation with low jitter for SONET/SDH (including FEC) , 10 Gb Ethernet, Fibre Channel, and DRFI/DOCSIS High-definition video frequency translation Wireless infrastructure Test and measurement (including handheld devices)

The ADCLK914 is an ultrafast clock/data buffer fabricated onthe Analog Devices, Inc., proprietary, complementary bipolar(XFCB-3) silicon-germanium (SiGe) process. The ADCLK914features high voltage differential signaling (HVDS) outputssuitable for driving the latest Analog Devices high speed digitalto-analogconverters (DACs). The ADCLK914 has a single,differential open-collector output.The ADCLK914 buffer operates up to 7.5 GHz with a 160 pspropagation delay and adds only 110 fs random jitter (RJ).The input has a center tapped, 100 Ω, on-chip terminationresistor and accepts LVPECL, CML, CMOS, LVTTL, or LVDS(ac-coupled only). A VREF pin is available for biasing ac-coupledinputs.The HVDS output stage is designed to directly drive 1.9 V eachside into 50 Ω terminated to VCC for a total differential outputswing of 3.8 V.The ADCLK914 is available in a 16-lead LFCSP. It is specifiedfor operation over the extended industrial temperature range of−40°C to +125°C.Applications Clock and data signal restoration High speed converter clocking Broadband communications Cellular infrastructure High speed line receivers ATE and high performance instrumentation Level shifting Threshold detection 

Timers & Support Products Low-Power General Purpose Timer

Delay Lines/Timing Elements 5-Tap Timing Element