Low Phase Noise, Fast Settling PLL Frequency Synthesizer Features: New, fast settling, fractional-N PLL architecture Single PLL replaces ping-pong synthesizers Frequency hop across GSM band in 5 µs with phase settled by 20 µs 0.5° rms phase error at 2 GHz RF output Digitally programmable output phase RF input range up to 3.5 GHz 3-wire serial interface On-chip, low noise differential amplifier Phase noise figure of merit: –216 dBc/Hz Loop filter design possible using ADIsimPLL™ Qualified for automotive applications

Low Phase Noise, Triple Output Clock Distribution Divider/Driver Features: Low Noise Clock Distribution: Suitable for High Speed/High Resolution ADC Clocking Additive Jitter < 20fsRMS (12kHz to 20MHz) Additive Jitter < 85fsRMS (10Hz to Nyquist) 1.8GHz Maximum Input Frequency (LTC6954-1 When DELAY = 0) 1.4GHz Maximum Input Frequency (LTC6954-1 When DELAY > 0, LTC6954-2, -3, -4) EZSync™ Clock Synchronization Compatible Three Independent, Low Noise Outputs Four Output Combinations Available Three Independent Programmable Dividers Covering All Integers From 1 to 63 Three Independent Programmable Delays Covering All Integers From 0 to 63 –40°C to 105°C Junction Temperature Range

Clock Buffer 8T79S308 1:8 UNIVERSAL DIFFERENTIAL FANOUT BUFFER

Clock Buffer 9QXL2000B DB2000Q

Clock Buffer LVCMOS 2:8 buffer (200 MHz), 2:1 LVCMOS input max, output enable (QFN16)

Timers MUR1 MULTIFUNCTION TIMER, 24VDC

Timers MBR1 TIMER FUNC B 24-240V DIN RL17.5MM

Clock Generators & Support Products Ultra low-jitter, 4-output, any-frequency (< 350MHz), any output clock generator

Clock Synthesizer/Jitter Cleaner CMOS output clock

Clock Buffer LVPECL 2:6 low-jitter buffer (200 MHz), 2:1 LVMCOS input