The ADN2812 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 automatically locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for ?40?C to +85?C ambient temperature, unless otherwise noted. This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power fiber optic receiver. The receiver front end, loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a user-adjustable threshold. The LOS detect circuit has hysteresis to prevent chatter at the output. The ADN2812 is available in a compact 5 mm ? 5 mm 32-lead lead frame chip scale package (LFCSP).ApplicationsSONET OC-1/OC-3/OC-12/OC-48 and all associated FEC rates Fibre Channel, 2? Fibre Channel, GbE, HDTV WDM transponders Regenerators/repeaters Test equipment Broadband cross-connects and routers

The ADN2816 provides the receiver functions of quantization and clock and data recovery for continuous data rates from 10 Mb/s to 675 Mb/s. The ADN2816 automatically locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for ?40?C to +85?C ambient temperature, unless otherwise noted.The ADN2816 is available in a compact 5 mm ? 5 mm 32-lead chip scale package.ApplicationsSONET OC-1/3/12 and all associated FEC rates Fibre Channel, ESCON, Fast Ethernet, SDI, etc. WDM transpondersRegenerators/repeatersTest equipmentBroadband cross-connects and routers

The ADF4371 allows implementation of fractional-N or Integer N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference frequency. The wideband microwave voltage controlled oscillator (VCO) design allows frequencies from 62.5 MHz to 32 GHz to be generated.The ADF4371 has an integrated VCO with a fundamental output frequency ranging from 4000 MHz to 8000 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allows the user to generate radio frequency (RF) output frequencies as low as 62.5 MHz at RF8x. A frequency multiplier at RF16x generates from 8 GHz to 16 GHz. A frequency quadrupler generates frequencies from 16 GHz to 32 GHz at RF32x. RFAUX8x duplicates the frequency range of RF8x or permits direct access to the VCO output. To suppress the unwanted products of frequency multiplication, a harmonic filter exists between the multipliers and the output stages of RF16x and RF32x.Control of all on-chip registers is through a 3-wire interface. The ADF4371 operates with analog and digital power suppliesranging from 3.15 V to 3.45 V, and 5 V for the VCO power supply. The ADF4371 also contains hardware and software power-down modes. APPLICATIONS Wireless infrastructure (multicarrier global system for mobile communication (MC-GSM), 5 G) Test equipment and instrumentation Clock generation Aerospace and defense

Together with an external loop filter and a voltage controlled crystal oscillator (VCXO), the HMC1031 forms a complete clock generator solution targeted at low frequency jitter attenuation and reference clock generation applications.The HMC1031 features a low power integer N divider, support-ing divide ratios of 1, 5, and 10, which is controlled via external hardware pins and requires no serial port.The integrated phase detector and charge pump are capable of operating at up to 140 MHz, and a maximum VCXO input of 500 MHz ensures frequency compliance with a wide variety of system clocks and VCXOs.Additional features include an integrated lock detect indicator available on a dedicated hardware pin, and a built in power-down mode.The HMC1031 is housed in an 8-lead MSOP package.APPLICATIONS Low jitter clock generation Low bandwidth (BW) jitter attenuation Low frequency phase-locked loops PLL Frequency translation Oven controlled crystal oscillator (OCXO) frequency multiplier Phase lock clean high frequency references to 10 MHz equipment

The HMC835LP6GE is a low noise, wide band, Fractional-N PLL that features an integrated VCO with a fundamental frequency of 2020 to 4100 MHz, and an integrated VCO Output Divider (divide by 2/4/6/.../60/62) that together enable the HMC835LP6GE to generate frequencies from 33 MHz to 4100 MHz. Integrated Phase Detector (PD) and a deltasigma modulator capable of operating at up to 100 MHz enable wider loop-bandwidths, faster frequency changes along with excellent spectral performance.Two independent RF outputs, with independent gain control, enable the HMC835LP6GE to distribute identical frequency and phase signals to multiple destinations, at optimal signal levels tailored to each output.External VCO input, allows the HMC835LP6GE to lock external VCOs, and enables cascaded LO architectures for MIMO radio applications. Two separate Charge Pump (CP) outputs enable separate loop filters optimized for both integrated and external VCOs, and seamless switching between integrated or external VCOs during operation. Programmable RF output phase feature can further phase adjust and synchronize multiple HMC835LP6GEs enabling scalable MIMO and beam-forming radio architectures.Additional features include configurable output mute function that mutes RF outputs during frequency changes, Exact Frequency Mode that enables the HMC835LP6GE to generate fractional frequencies with 0 Hz frequency error, and the ability to synchronously change frequencies without changing the phase of the output signal.Applications MIMO Radio Architectures Cellular Infrastructure Cellular backhaul Communications Test Equipment CATV Equipment Phased Array Applications? DDS Replacement

The LTC6947 is a high performance, low noise, 6GHz phase-locked loop (PLL), including a reference divider, phase-frequency detector (PFD), ultralow noise charge pump, fractional feedback divider, and VCO output divider.The fractional divider uses an advanced, 4th order ?? modulator which provides exceptionally low spurious levels. This allows wide loop bandwidths, producing extremely low integrated phase noise values.The programmable VCO output divider, with a range of 1 through 6, extends the output frequency range. The differential, low-noise output buffer has user-programmable output power ranging from ?4.3dBm to +4.5dBm, and may be muted through either a digital input pin or software.The ultralow noise charge pump contains selectable high and low voltage clamps useful for VCO monitoring, and also may be set to provide a V+/2 bias.All device settings are controlled through a SPI-compatible serial port.Applications Wireless Basestations (LTE, WiMAX, W-CDMA, PCS) Broadband Wireless Access Microwave Data Links Military and Secure Radio Test and Measurement

The ADF5000 prescaler is a low noise, low power, fixed RF divider block that can be used to divide down frequencies as high as 18 GHz to a lower frequency suitable for input to a PLL IC, such as the?ADF4156 or the ADF4106. The ADF5000 provides a divide-by-2 function. The ADF5000 operates from a 3.3 V supply and has differential 100 ? RF outputs to allow direct interface to the differential RF inputs of PLLs such as the ADF4156 and ADF4106.Applications PLL frequency range extender Point-to-point radios VSAT radios Communications test equipment?

Demonstration circuit 1562B is an engineering tool to design and evaluate the LTC699X-X family of TimerBlox® circuits. The center section of the board contains a preconfigured TimerBlox function. DC1562B comes in twelve timing function variations as outlined in Table 1.

6.2 GHz Fractional-N Frequency Synthesizer Features: RF bandwidth to 6.2 GHz 2.7 V to 3.3 V power supply Separate VP allows extended tuning voltage Programmable fractional modulus Programmable charge pump currents 3-wire serial interface Digital lock detect Power-down mode Pin compatible with the ADF4110, ADF4111, ADF4112, ADF4113, ADF4106, ADF4153, and ADF4154 frequency synthesizers Programmable RF output phase Loop filter design possible with ADIsimPLL Cycle slip reduction for faster lock times

Low Phase Noise, Triple Output Clock Distribution Divider/Driver Features: Low Noise Clock Distribution: Suitable for High Speed/High Resolution ADC Clocking Additive Jitter < 20fsRMS (12kHz to 20MHz) Additive Jitter < 85fsRMS (10Hz to Nyquist) 1.8GHz Maximum Input Frequency (LTC6954-1 When DELAY = 0) 1.4GHz Maximum Input Frequency (LTC6954-1 When DELAY > 0, LTC6954-2, -3, -4) EZSync™ Clock Synchronization Compatible Three Independent, Low Noise Outputs Four Output Combinations Available Three Independent Programmable Dividers Covering All Integers From 1 to 63 Three Independent Programmable Delays Covering All Integers From 0 to 63 –40°C to 105°C Junction Temperature Range