Clock Buffer Universal 2:10 low-jitter clock buffer/level translator with individual OE

Clock Synthesizer/Jitter Cleaner Any-frequency jitter attenuating clock

Clock Synthesizer/Jitter Cleaner HDTV CLOCK SYNTHESIZER

Clock Drivers & Distribution CLK DRIVER, 3.3V TURBO CLK

BUFFERS & TRANSCEIVERS;

Clock Synthesizer/Jitter Cleaner SMU for IEEE 1588 Synchronous Ethernet

Low Phase Noise, Triple Output Clock Distribution Divider/Driver Features: Low Noise Clock Distribution: Suitable for High Speed/High Resolution ADC Clocking Additive Jitter < 20fsRMS (12kHz to 20MHz) Additive Jitter < 85fsRMS (10Hz to Nyquist) 1.8GHz Maximum Input Frequency (LTC6954-1 When DELAY = 0) 1.4GHz Maximum Input Frequency (LTC6954-1 When DELAY > 0, LTC6954-2, -3, -4) EZSync™ Clock Synchronization Compatible Three Independent, Low Noise Outputs Four Output Combinations Available Three Independent Programmable Dividers Covering All Integers From 1 to 63 Three Independent Programmable Delays Covering All Integers From 0 to 63 –40°C to 105°C Junction Temperature Range

Clock Generators & Support Products 4-output, any frequency (< 350 MHz), any output, clock generator (reference input)

Translation Loop, PLL, VCO Module Features: RF output frequency range: 62.5 MHz to 8000 MHz 9 fs rms jitter at 8 GHz output 17 dBm IF output power at 6 GHz RF output 90 dBc LO_IN to RF output 90 dBc spurious-free dynamic range Low phase noise, voltage controlled oscillator Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output 3.3 V analog, digital, and mixer power supplies 5 V amplifier and VCO power supply RF output mute function 18.00 mm × 18.00 mm, 80-terminal LGA_CAV Supported in the ADIsimPLL design tool

PCM JITTER ATTENUATOR ROHS COMPLIANT: YES