The LTC2261-14/LTC2260-14/LTC2259-14 are sampling 14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 73.4dB SNR and 85dB spurious free dynamic range (SFDR). Ultralow jitter of 0.17psRMS allows undersampling of IF frequencies with excellent noise performance.DC specs include ±1LSB INL (typical), ±0.3LSB DNL (typical) and no missing codes over temperature. The transition noise is a low 1.2LSBRMS.The digital outputs can be either full rate CMOS, double data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V.The ENC+ and ENC– inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. Bits LTC2260-12 12 LTC2260-14 14  Applications Communications Cellular Base Stations Software Defined Radios Portable Medical Imaging Multi-Channel Data Acquisition Nondestructive Testing

The LTC2261-12/LTC2260-12/LTC2259-12 are sampling 12-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 70.8dB SNR and 85dB spurious free dynamic range (SFDR). Ultralow jitter of 0.17psRMS allows undersampling of IF frequencies with excellent noise performance.DC specs include ±0.3LSB INL (typical), ±0.1LSB DNL (typical) and no missing codes over temperature. The transition noise is a low 0.3LSBRMS.The digital outputs can be either full-rate CMOS, double-data rate CMOS, or double-data rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V.The ENC+ and ENC– inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. Bits LTC2260-12 12 LTC2260-14 14 Applications Communications Cellular Base Stations Software Defined Radios Portable Medical Imaging Multi-Channel Data Acquisition Nondestructive Testing

The LTC2261-14/LTC2260-14/LTC2259-14 are sampling 14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 73.4dB SNR and 85dB spurious free dynamic range (SFDR). Ultralow jitter of 0.17psRMS allows undersampling of IF frequencies with excellent noise performance.DC specs include ±1LSB INL (typical), ±0.3LSB DNL (typical) and no missing codes over temperature. The transition noise is a low 1.2LSBRMS.The digital outputs can be either full-rate CMOS, doubledata rate CMOS, or double-data rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V.The ENC+ and ENC– inputs may be driven differentially or single ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. Bits LTC2261-12 12 LTC2261-14 14 Applications Communications Cellular Base Stations Software Defined Radios Portable Medical Imaging Multi-Channel Data Acquisition Nondestructive Testing

The LTC2216/LTC2215 are 80Msps/65Msps sampling 16- bit A/D converters designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 400MHz. The input range of the ADC is fixed at 2.75VP-P.The LTC2216/LTC2215 are perfect for demanding communications applications, with AC performance that includes 81.5dBFS noise floor and 100dB spurious free dynamic range (SFDR). Ultra low jitter of 85fsRMS allows undersampling of high input frequencies while maintaining excellent noise performance. Maximum DC specs include ±3.5LSB INL, ±1LSB DNL (no missing codes). The digital output can be either differential LVDS or single-ended CMOS. There are two format options for the CMOS outputs: a single bus running at the full data rate or demultiplexed buses running at half data rate. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V. The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles.Applications Telecommunications Receivers Cellular Base Stations Spectrum Analysis Imaging Systems ATE

Data Conversion IC Development Tools LTC2258-12: 12-bit 65Msps ADC, LVDS Outp

Data Conversion IC Development Tools LTM9012 14-Bit, 125Msps Quad uModule ADC + Driver, req DC1371 and DC1075

ADC, 24BIT, 2.4KSPS, LFCSP-EP-32;

Data Conversion IC Development Tools USB Data Acquisition Controller, for PSc

The AD5684R nanoDAC+™ is a quad, 12-bit, rail-to-rail, voltage output DAC. The device includes a 2.5V, 2ppm/˚C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5V (gain=1) or 5V (gain=2). The device operates from a single 2.7 V to 5.5 V supply, is guaranteed monotonic by design and exhibits less than 0.1% FSR gain error and 1.5mV offset error performance. The device is available in a 3mm X 3mm LFCSP and a TSSOP package.The AD5684R also incorporates a power-on-reset circuit and a RSTSEL pin that ensures the DAC outputs power up to zero-scale or midscale, and remain there until a valid write takes place. Each device contains a per-channel power-down feature that reduces the current consumption of the device to 4 uA at 3 V while in power-down mode.The AD5684R employs a versatile SPI interface that operates at clock rates up to 50 MHz and includes a VLOGIC pin intended for 1.8V/3V/5V logic.Product Highlights High relative accuracy: AD5684R (12-bit): ±1LSB INL max Low drift on-chip reference: 2.5V, 2ppm/°C temperature drift Two package options: 3mm × 3mm 16-lead LFCSP or 16-lead TSSOPApplications Optical transceivers Base-station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems

The AD5689/AD5687 members of the nanoDAC+™ family arelow power, dual, 16-/12-bit, buffered voltage output digital-to-analogconverters (DACs). The devices include a gain select pingiving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). TheAD5689/AD5687 operate from a single 2.7 V to 5.5 V supply, areguaranteed monotonic by design, and exhibit less than 0.1% FSRgain error and 1.5 mV offset error performance. Both devices areavailable in a 3 mm × 3 mm LFCSP and a TSSOP package.The AD5689/AD5687 also incorporate a power-on reset circuitand a RSTSEL pin that ensure that the DAC outputs power upto zero scale or midscale and remain there until a valid writetakes place. Each part contains a per channel power-down featurethat reduces the current consumption of the device to 4 µA at3 V while in power-down mode.The AD5689/AD5687 uses a versatile serial peripheral interfacethat operates at clock rates up to 50 MHz. Both devices containa VLOGIC pin that is intended for 1.8 V/3 V/5 V logic.Product Highlights High Relative Accuracy (INL). AD5687 (12-bit): ±1 LSB maximum Excellent DC Performance. Total unadjusted error: ±0.1% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.1% of FSR maximum Two Package Options. 3 mm × 3 mm, 16-lead LFCSP or 16-lead TSSOPApplications Optical transceivers Base station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems